| 1 | /**
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| 2 | * This file has no copyright assigned and is placed in the Public Domain.
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| 3 | * This file is part of the mingw-w64 runtime package.
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| 4 | * No warranty is given; refer to the file DISCLAIMER.PD within this package.
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| 5 | */
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| 6 | #define SHADOW_IRQL_IMPLEMENTATION 1
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| 7 |
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| 8 | #define PS0 0x0001
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| 9 | #define PS1 0x0002
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| 10 | #define PS2 0x0004
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| 11 | #define PS3 0x0008
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| 12 | #define PS4 0x0010
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| 13 | #define PS5 0x0020
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| 14 |
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| 15 | #define PRP 0x0080
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| 16 |
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| 17 | #define PT0 0x0040
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| 18 | #define PT1 0x0100
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| 19 | #define PT2 0x0200
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| 20 | #define PT3 0x0400
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| 21 | #define PT4 0x0800
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| 22 | #define PT5 0x1000
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| 23 | #define PT6 0x2000
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| 24 | #define PT7 0x4000
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| 25 | #define PT8 0x8000
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| 26 |
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| 27 | #define NOM_BS0 0x0001
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| 28 | #define NOM_BS1 0x0002
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| 29 | #define NOM_BS2 0x0004
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| 30 | #define NOM_BS3 0x0008
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| 31 | #define NOM_BS4 0x0010
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| 32 | #define NOM_BS5 0x0020
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| 33 |
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| 34 | #define NOM_BRP 0x0080
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| 35 |
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| 36 | #define NOM_BT0 0x0040
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| 37 | #define NOM_BT1 0x0100
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| 38 | #define NOM_BT2 0x0200
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| 39 | #define NOM_BT3 0x0400
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| 40 | #define NOM_BT4 0x0800
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| 41 | #define NOM_BT5 0x1000
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| 42 | #define NOM_BT6 0x2000
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| 43 | #define NOM_BT7 0x4000
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| 44 | #define NOM_BT8 0x8000
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| 45 |
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| 46 | #define PSR_MBZ4 0
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| 47 | #define PSR_BE 1
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| 48 | #define PSR_UP 2
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| 49 | #define PSR_AC 3
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| 50 | #define PSR_MFL 4
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| 51 | #define PSR_MFH 5
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| 52 |
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| 53 | #define PSR_MBZ0 6
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| 54 | #define PSR_MBZ0_V 0x7fll
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| 55 |
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| 56 | #define PSR_IC 13
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| 57 | #define PSR_I 14
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| 58 | #define PSR_PK 15
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| 59 | #define PSR_MBZ1 16
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| 60 | #define PSR_MBZ1_V 0x1ll
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| 61 | #define PSR_DT 17
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| 62 | #define PSR_DFL 18
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| 63 | #define PSR_DFH 19
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| 64 | #define PSR_SP 20
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| 65 | #define PSR_PP 21
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| 66 | #define PSR_DI 22
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| 67 | #define PSR_SI 23
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| 68 | #define PSR_DB 24
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| 69 | #define PSR_LP 25
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| 70 | #define PSR_TB 26
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| 71 | #define PSR_RT 27
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| 72 |
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| 73 | #define PSR_MBZ2 28
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| 74 | #define PSR_MBZ2_V 0xfll
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| 75 |
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| 76 | #define PSR_CPL 32
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| 77 | #define PSR_CPL_LEN 2
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| 78 | #define PSR_IS 34
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| 79 | #define PSR_MC 35
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| 80 | #define PSR_IT 36
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| 81 | #define PSR_ID 37
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| 82 | #define PSR_DA 38
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| 83 | #define PSR_DD 39
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| 84 | #define PSR_SS 40
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| 85 | #define PSR_RI 41
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| 86 | #define PSR_RI_LEN 2
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| 87 | #define PSR_ED 43
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| 88 | #define PSR_BN 44
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| 89 | #define PSR_IA 45
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| 90 |
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| 91 | #define PSR_MBZ3 46
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| 92 | #define PSR_MBZ3_V 0x3ffffll
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| 93 |
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| 94 | #define PL_KERNEL 0
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| 95 | #define PL_USER 3
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| 96 |
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| 97 | #define IS_EM 0
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| 98 | #define IS_IA 1
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| 99 |
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| 100 | #define FPSR_VD 0
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| 101 | #define FPSR_DD 1
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| 102 | #define FPSR_ZD 2
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| 103 | #define FPSR_OD 3
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| 104 | #define FPSR_UD 4
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| 105 | #define FPSR_ID 5
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| 106 |
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| 107 | #define FPSR_FTZ0 6
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| 108 | #define FPSR_WRE0 7
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| 109 | #define FPSR_PC0 8
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| 110 | #define FPSR_RC0 10
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| 111 | #define FPSR_TD0 12
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| 112 |
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| 113 | #define FPSR_V0 13
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| 114 | #define FPSR_D0 14
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| 115 | #define FPSR_Z0 15
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| 116 | #define FPSR_O0 16
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| 117 | #define FPSR_U0 17
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| 118 | #define FPSR_I0 18
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| 119 |
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| 120 | #define FPSR_FTZ1 19
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| 121 | #define FPSR_WRE1 20
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| 122 | #define FPSR_PC1 21
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| 123 | #define FPSR_RC1 23
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| 124 | #define FPSR_TD1 25
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| 125 |
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| 126 | #define FPSR_V1 26
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| 127 | #define FPSR_D1 27
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| 128 | #define FPSR_Z1 28
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| 129 | #define FPSR_O1 29
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| 130 | #define FPSR_U1 30
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| 131 | #define FPSR_I1 31
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| 132 |
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| 133 | #define FPSR_FTZ2 32
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| 134 | #define FPSR_WRE2 33
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| 135 | #define FPSR_PC2 34
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| 136 | #define FPSR_RC2 36
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| 137 | #define FPSR_TD2 38
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| 138 |
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| 139 | #define FPSR_V2 39
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| 140 | #define FPSR_D2 40
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| 141 | #define FPSR_Z2 41
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| 142 | #define FPSR_O2 42
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| 143 | #define FPSR_U2 43
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| 144 | #define FPSR_I2 44
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| 145 |
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| 146 | #define FPSR_FTZ3 45
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| 147 | #define FPSR_WRE3 46
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| 148 | #define FPSR_PC3 47
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| 149 | #define FPSR_RC3 49
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| 150 | #define FPSR_TD3 51
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| 151 |
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| 152 | #define FPSR_V3 52
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| 153 | #define FPSR_D3 53
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| 154 | #define FPSR_Z3 54
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| 155 | #define FPSR_O3 55
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| 156 | #define FPSR_U3 56
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| 157 | #define FPSR_I3 57
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| 158 |
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| 159 | #define FPSR_MBZ0 58
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| 160 | #define FPSR_MBZ0_V 0x3fll
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| 161 |
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| 162 | #define FPSR_FOR_KERNEL 0x9804C0270033F
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| 163 |
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| 164 | #define TPR_MIC 4
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| 165 | #define TPR_MIC_LEN 4
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| 166 |
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| 167 | #define TPR_MMI 16
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| 168 |
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| 169 | #define TPR_IRQL_SHIFT TPR_MIC
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| 170 |
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| 171 | #define VECTOR_IRQL_SHIFT TPR_IRQL_SHIFT
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| 172 |
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| 173 | #define ISR_CODE 0
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| 174 | #define ISR_CODE_LEN 16
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| 175 | #define ISR_CODE_MASK 0xFFFF
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| 176 | #define ISR_NA_CODE_MASK 0xF
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| 177 | #define ISR_IA_VECTOR 16
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| 178 | #define ISR_IA_VECTOR_LEN 8
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| 179 |
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| 180 | #define ISR_MBZ0 24
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| 181 | #define ISR_MBZ0_V 0xff
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| 182 | #define ISR_X 32
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| 183 | #define ISR_W 33
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| 184 | #define ISR_R 34
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| 185 | #define ISR_NA 35
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| 186 | #define ISR_SP 36
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| 187 | #define ISR_RS 37
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| 188 | #define ISR_IR 38
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| 189 | #define ISR_NI 39
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| 190 |
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| 191 | #define ISR_MBZ1 40
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| 192 | #define ISR_EI 41
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| 193 | #define ISR_ED 43
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| 194 |
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| 195 | #define ISR_MBZ2 44
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| 196 | #define ISR_MBZ2_V 0xfffff
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| 197 |
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| 198 | #define ISR_TPA 0
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| 199 | #define ISR_FC 1
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| 200 | #define ISR_PROBE 2
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| 201 | #define ISR_TAK 3
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| 202 | #define ISR_LFETCH 4
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| 203 | #define ISR_PROBE_FAULT 5
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| 204 |
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| 205 | #define ISR_ILLEGAL_OP 0
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| 206 | #define ISR_PRIV_OP 1
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| 207 | #define ISR_PRIV_REG 2
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| 208 | #define ISR_RESVD_REG 3
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| 209 | #define ISR_ILLEGAL_ISA 4
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| 210 | #define ISR_ILLEGAL_HAZARD 8
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| 211 |
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| 212 | #define ISR_NAT_REG 1
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| 213 | #define ISR_NAT_PAGE 2
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| 214 |
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| 215 | #define ISR_FP_TRAP 0
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| 216 |
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| 217 | #define ISR_LP_TRAP 1
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| 218 |
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| 219 | #define ISR_TB_TRAP 2
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| 220 |
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| 221 | #define ISR_SS_TRAP 3
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| 222 |
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| 223 | #define ISR_UI_TRAP 4
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| 224 |
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| 225 | #define DCR_PP 0
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| 226 | #define DCR_BE 1
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| 227 | #define DCR_LC 2
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| 228 |
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| 229 | #define DCR_DM 8
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| 230 | #define DCR_DP 9
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| 231 | #define DCR_DK 10
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| 232 | #define DCR_DX 11
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| 233 | #define DCR_DR 12
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| 234 | #define DCR_DA 13
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| 235 | #define DCR_DD 14
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| 236 | #define DCR_DEFER_ALL 0x7f00
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| 237 |
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| 238 | #define DCR_MBZ1 2
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| 239 | #define DCR_MBZ1_V 0xffffffffffffll
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| 240 |
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| 241 | #define RSC_MODE 0
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| 242 | #define RSC_PL 2
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| 243 | #define RSC_BE 4
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| 244 |
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| 245 | #define RSC_MBZ0 5
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| 246 | #define RSC_MBZ0_V 0x3ff
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| 247 | #define RSC_LOADRS 16
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| 248 | #define RSC_LOADRS_LEN 14
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| 249 |
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| 250 | #define RSC_MBZ1 30
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| 251 | #define RSC_MBZ1_LEN 34
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| 252 | #define RSC_MBZ1_V 0x3ffffffffll
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| 253 |
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| 254 | #define RSC_MODE_LY (0x0)
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| 255 |
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| 256 | #define RSC_MODE_SI (0x1)
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| 257 |
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| 258 | #define RSC_MODE_LI (0x2)
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| 259 |
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| 260 | #define RSC_MODE_EA (0x3)
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| 261 |
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| 262 | #define RSC_BE_LITTLE 0
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| 263 | #define RSC_BE_BIG 1
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| 264 |
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| 265 | #define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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| 266 |
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| 267 | #define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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| 268 |
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| 269 | #define IFS_IFM 0
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| 270 | #define IFS_IFM_LEN 38
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| 271 | #define IFS_MBZ0 38
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| 272 | #define IFS_MBZ0_V 0x1ffffffll
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| 273 | #define IFS_V 63
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| 274 | #define IFS_V_LEN 1
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| 275 |
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| 276 | #define IFS_VALID 1
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| 277 |
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| 278 | #define PFS_PPL 62
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| 279 | #define PFS_PPL_LEN PSR_CPL_LEN
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| 280 | #define PFS_EC_SHIFT 52
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| 281 | #define PFS_EC_SIZE 6
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| 282 | #define PFS_EC_MASK 0x3F
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| 283 | #define PFS_SIZE_SHIFT 7
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| 284 | #define PFS_SIZE_MASK 0x7F
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| 285 | #define NAT_BITS_PER_RNAT_REG 63
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| 286 | #define RNAT_ALIGNMENT (NAT_BITS_PER_RNAT_REG << 3)
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| 287 |
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| 288 | #define RR_VE 0
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| 289 | #define RR_MBZ0 1
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| 290 | #define RR_PS 2
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| 291 | #define RR_PS_LEN 6
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| 292 | #define RR_RID 8
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| 293 | #define RR_RID_LEN 24
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| 294 | #define RR_MBZ1 32
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| 295 |
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| 296 | #define RR_INDEX 61
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| 297 | #define RR_INDEX_LEN 3
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| 298 |
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| 299 | #define RR_PS_VE ((PAGE_SHIFT<<RR_PS) | (1<<RR_VE))
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| 300 |
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| 301 | #define NT_RR_SIZE 4
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| 302 |
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| 303 | #define RR_SIZE 8
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| 304 |
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| 305 | #define PKR_V 0
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| 306 | #define PKR_WD 1
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| 307 | #define PKR_RD 2
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| 308 | #define PKR_XD 3
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| 309 | #define PKR_MBZ0 4
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| 310 | #define PKR_KEY 8
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| 311 | #define PKR_KEY_LEN 24
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| 312 | #define PKR_MBZ1 32
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| 313 |
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| 314 | #define PKR_VALID (1<<PKR_V)
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| 315 |
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| 316 | #define PKRNUM 16
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| 317 |
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| 318 | #define ITIR_RV0 0
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| 319 | #define ITIR_PS 2
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| 320 | #define ITIR_KEY 8
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| 321 | #define ITIR_RV1 32
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| 322 |
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| 323 | #define IDTR_MBZ0 0
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| 324 | #define IDTR_PS 2
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| 325 | #define IDTR_KEY 8
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| 326 | #define IDTR_MBZ1 32
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| 327 | #define IDTR_IGN0 48
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| 328 | #define IDTR_PPN 56
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| 329 | #define IDTR_MBZ2 63
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| 330 |
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| 331 | #define IITR_MBZ0 IDTR_MBZ0
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| 332 | #define IITR_PS IDTR_PS
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| 333 | #define IITR_KEY IDTR_KEY
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| 334 | #define IITR_MBZ1 IDTR_MBZ1
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| 335 | #define IITR_IGN0 IDTR_IGN0
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| 336 | #define IITR_PPN IDTR_PPN
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| 337 | #define IITR_MBZ2 IDTR_MBZ2
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| 338 |
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| 339 | #define IITR_PPN_MASK 0x7FFF000000000000
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| 340 | #define IITR_ATTRIBUTE_PPN_MASK 0x0003FFFFFFFFF000
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| 341 |
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| 342 | #define TR_P 0
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| 343 | #define TR_RV0 1
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| 344 | #define TR_MA 2
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| 345 | #define TR_A 5
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| 346 | #define TR_D 6
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| 347 | #define TR_PL 7
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| 348 | #define TR_AR 9
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| 349 | #define TR_PPN 13
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| 350 | #define TR_RV1 50
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| 351 | #define TR_ED 52
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| 352 | #define TR_IGN0 53
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| 353 |
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| 354 | #define TR_VALUE(ed,ppn,ar,pl,d,a,ma,p) ((ed << TR_ED) | (ppn & IITR_ATTRIBUTE_PPN_MASK) | (ar << TR_AR) | (pl << TR_PL) | (d << TR_D) | (a << TR_A) | (ma << TR_MA) | (p << TR_P))
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| 355 |
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| 356 | #define ITIR_VALUE(key,ps) ((ps << ITIR_PS) | (key << ITIR_KEY))
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| 357 |
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| 358 | #define PS_4K 0xC
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| 359 | #define PS_8K 0xD
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| 360 | #define PS_16K 0xE
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| 361 | #define PS_64K 0x10
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| 362 | #define PS_256K 0x12
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| 363 | #define PS_1M 0x14
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| 364 | #define PS_4M 0x16
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| 365 | #define PS_16M 0x18
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| 366 | #define PS_64M 0x1a
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| 367 | #define PS_256M 0x1c
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| 368 |
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| 369 | #define NUMBER_OF_DEBUG_REGISTER_PAIRS 4
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| 370 |
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| 371 | #define DR_MASK 0
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| 372 | #define DR_MASK_LEN 56
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| 373 | #define DR_PLM0 56
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| 374 | #define DR_PLM1 57
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| 375 | #define DR_PLM2 58
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| 376 | #define DR_PLM3 59
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| 377 | #define DR_IG 60
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| 378 | #define DR_RW 62
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| 379 | #define DR_RW_LEN 2
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| 380 | #define DR_X 63
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| 381 |
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| 382 | #define NUMBER_OF_PERFMON_REGISTER_PAIRS 4
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| 383 |
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| 384 | #define MASK_IA64(bp,value) (value << bp)
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| 385 |
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| 386 | #define APC_VECTOR APC_LEVEL << VECTOR_IRQL_SHIFT
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| 387 | #define DISPATCH_VECTOR DISPATCH_LEVEL << VECTOR_IRQL_SHIFT
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| 388 |
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| 389 | #define OFFSET_VECTOR_BREAK 0x2800
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| 390 | #define OFFSET_VECTOR_EXT_INTERRUPT 0x2c00
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| 391 | #define OFFSET_VECTOR_EXC_GENERAL 0x4400
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| 392 |
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| 393 | #define PAGEMASK_4KB 0x0
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| 394 | #define PAGEMASK_16KB 0x3
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| 395 | #define PAGEMASK_64KB 0xf
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| 396 | #define PAGEMASK_256KB 0x3f
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| 397 | #define PAGEMASK_1MB 0xff
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| 398 | #define PAGEMASK_4MB 0x3ff
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| 399 | #define PAGEMASK_16MB 0xfff
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| 400 |
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| 401 | #define PRIMARY_CACHE_INVALID 0x0
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| 402 | #define PRIMARY_CACHE_SHARED 0x1
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| 403 | #define PRIMARY_CACHE_CLEAN_EXCLUSIVE 0x2
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| 404 | #define PRIMARY_CACHE_DIRTY_EXCLUSIVE 0x3
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| 405 |
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| 406 | #define PS_SHIFT 2
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| 407 | #define PS_LEN 6
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| 408 | #define PTE_VALID_MASK 1
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| 409 | #define PTE_ACCESS_MASK 0x20
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| 410 | #define PTE_NOCACHE 0x10
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| 411 | #define PTE_CACHE_SHIFT 2
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| 412 | #define PTE_CACHE_LEN 3
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| 413 | #define PTE_LARGE_PAGE 54
|
|---|
| 414 | #define PTE_PFN_SHIFT 8
|
|---|
| 415 | #define PTE_PFN_LEN 24
|
|---|
| 416 | #define PTE_ATTR_SHIFT 1
|
|---|
| 417 | #define PTE_ATTR_LEN 5
|
|---|
| 418 | #define PTE_PS 55
|
|---|
| 419 | #define PTE_OFFSET_LEN 10
|
|---|
| 420 | #define PDE_OFFSET_LEN 10
|
|---|
| 421 | #define VFN_LEN 19
|
|---|
| 422 | #define VFN_LEN64 24
|
|---|
| 423 | #define TB_USER_MASK 0x180
|
|---|
| 424 | #define PTE_DIRTY_MASK 0x40
|
|---|
| 425 | #define PTE_WRITE_MASK 0x400
|
|---|
| 426 | #define PTE_EXECUTE_MASK 0x200
|
|---|
| 427 | #define PTE_CACHE_MASK 0x0
|
|---|
| 428 | #define PTE_EXC_DEFER 0x10000000000000
|
|---|
| 429 |
|
|---|
| 430 | #define VALID_KERNEL_PTE (PTE_VALID_MASK|PTE_ACCESS_MASK|PTE_WRITE_MASK|PTE_CACHE_MASK|PTE_DIRTY_MASK)
|
|---|
| 431 | #define VALID_KERNEL_EXECUTE_PTE (PTE_VALID_MASK|PTE_ACCESS_MASK|PTE_EXECUTE_MASK|PTE_WRITE_MASK|PTE_CACHE_MASK|PTE_DIRTY_MASK|PTE_EXC_DEFER)
|
|---|
| 432 | #define PTE_VALID 0
|
|---|
| 433 | #define PTE_ACCESS 5
|
|---|
| 434 | #define PTE_OWNER 7
|
|---|
| 435 | #define PTE_WRITE 10
|
|---|
| 436 | #define PTE_LP_CACHE_SHIFT 53
|
|---|
| 437 | #define ATE_INDIRECT 62
|
|---|
| 438 | #define ATE_MASK 0xFFFFFFFFFFFFF9DE
|
|---|
| 439 | #define ATE_MASK0 0x621
|
|---|
| 440 | #define PAGE4K_SHIFT 12
|
|---|
| 441 | #define ALT4KB_BASE 0x6FC00000000
|
|---|
| 442 | #define ALT4KB_END 0x6FC00800000
|
|---|
| 443 |
|
|---|
| 444 | #define VRN_SHIFT 61
|
|---|
| 445 | #define KSEG3_VRN 4
|
|---|
| 446 | #define KSEG4_VRN 5
|
|---|
| 447 | #define MAX_PHYSICAL_SHIFT 44
|
|---|
| 448 |
|
|---|
| 449 | #define DISABLE_TAR_FIX 0
|
|---|
| 450 | #define DISABLE_BTB_FIX 1
|
|---|
| 451 | #define DISABLE_DATA_BP_FIX 2
|
|---|
| 452 | #define DISABLE_DET_STALL_FIX 3
|
|---|
| 453 | #define ENABLE_FULL_DISPERSAL 4
|
|---|
| 454 | #define ENABLE_TB_BROADCAST 5
|
|---|
| 455 | #define DISABLE_CPL_FIX 6
|
|---|
| 456 | #define ENABLE_POWER_MANAGEMENT 7
|
|---|
| 457 | #define DISABLE_IA32BR_FIX 8
|
|---|
| 458 | #define DISABLE_L1_BYPASS 9
|
|---|
| 459 | #define DISABLE_VHPT_WALKER 10
|
|---|
| 460 | #define DISABLE_IA32RSB_FIX 11
|
|---|
| 461 | #define DISABLE_INTERRUPTION_LOG 13
|
|---|
| 462 | #define DISABLE_UNSAFE_FILL 14
|
|---|
| 463 | #define DISABLE_STORE_UPDATE 15
|
|---|
| 464 | #define ENABLE_HISTORY_BUFFER 16
|
|---|
| 465 |
|
|---|
| 466 | #define BL_4M 0x00400000
|
|---|
| 467 | #define BL_16M 0x01000000
|
|---|
| 468 | #define BL_20M 0x01400000
|
|---|
| 469 | #define BL_24M 0x01800000
|
|---|
| 470 | #define BL_28M 0x01C00000
|
|---|
| 471 | #define BL_32M 0x02000000
|
|---|
| 472 | #define BL_36M 0x02400000
|
|---|
| 473 | #define BL_40M 0x02800000
|
|---|
| 474 | #define BL_48M 0x03000000
|
|---|
| 475 | #define BL_64M 0x04000000
|
|---|
| 476 | #define BL_80M 0x05000000
|
|---|
| 477 | #define BL_128M 0x08000000
|
|---|
| 478 |
|
|---|
| 479 | #define TR_INFO_TABLE_SIZE 10
|
|---|
| 480 |
|
|---|
| 481 | #define BL_SAL_INDEX 0
|
|---|
| 482 | #define BL_KERNEL_INDEX 1
|
|---|
| 483 | #define BL_DRIVER0_INDEX 2
|
|---|
| 484 | #define BL_DRIVER1_INDEX 3
|
|---|
| 485 | #define BL_DECOMPRESS_INDEX 4
|
|---|
| 486 | #define BL_IO_PORT_INDEX 5
|
|---|
| 487 | #define BL_PAL_INDEX 6
|
|---|
| 488 | #define BL_LOADER_INDEX 7
|
|---|
| 489 |
|
|---|
| 490 | #define DTR_KIPCR_INDEX 0
|
|---|
| 491 | #define DTR_KERNEL_INDEX 1
|
|---|
| 492 |
|
|---|
| 493 | #define DTR_DRIVER0_INDEX 2
|
|---|
| 494 | #define DTR_KTBASE_INDEX 2
|
|---|
| 495 |
|
|---|
| 496 | #define DTR_DRIVER1_INDEX 3
|
|---|
| 497 | #define DTR_UTBASE_INDEX 3
|
|---|
| 498 | #define DTR_VIDEO_INDEX 3
|
|---|
| 499 |
|
|---|
| 500 | #define DTR_KIPCR2_INDEX 4
|
|---|
| 501 | #define DTR_STBASE_INDEX 4
|
|---|
| 502 |
|
|---|
| 503 | #define DTR_IO_PORT_INDEX 5
|
|---|
| 504 |
|
|---|
| 505 | #define DTR_KTBASE_INDEX_TMP 6
|
|---|
| 506 | #define DTR_HAL_INDEX 6
|
|---|
| 507 | #define DTR_PAL_INDEX 6
|
|---|
| 508 |
|
|---|
| 509 | #define DTR_UTBASE_INDEX_TMP 7
|
|---|
| 510 | #define DTR_LOADER_INDEX 7
|
|---|
| 511 | #define DTR_UTBASE_INDEX_TMP 7
|
|---|
| 512 |
|
|---|
| 513 | #define ITR_EPC_INDEX 0
|
|---|
| 514 |
|
|---|
| 515 | #define ITR_KERNEL_INDEX 1
|
|---|
| 516 |
|
|---|
| 517 | #define ITR_DRIVER0_INDEX 2
|
|---|
| 518 |
|
|---|
| 519 | #define ITR_DRIVER1_INDEX 3
|
|---|
| 520 |
|
|---|
| 521 | #define ITR_HAL_INDEX 4
|
|---|
| 522 | #define ITR_PAL_INDEX 4
|
|---|
| 523 |
|
|---|
| 524 | #define ITR_LOADER_INDEX 7
|
|---|
| 525 |
|
|---|
| 526 | #define MEM_4K 0x1000
|
|---|
| 527 | #define MEM_8K 0x2000
|
|---|
| 528 | #define MEM_16K 0x4000
|
|---|
| 529 | #define MEM_64K 0x10000
|
|---|
| 530 | #define MEM_256K 0x40000
|
|---|
| 531 | #define MEM_1M 0x100000
|
|---|
| 532 | #define MEM_4M 0x400000
|
|---|
| 533 | #define MEM_16M 0x1000000
|
|---|
| 534 | #define MEM_64M 0x4000000
|
|---|
| 535 | #define MEM_256M 0x10000000
|
|---|
| 536 |
|
|---|
| 537 | #define MEM_SIZE_TO_PS(MemSize,TrPageSize) if (MemSize <= MEM_4K) { TrPageSize = PS_4K; } else if (MemSize <= MEM_8K) { TrPageSize = PS_8K; } else if (MemSize <= MEM_16K) { TrPageSize = PS_16K; } else if (MemSize <= MEM_64K) { TrPageSize = PS_64K; } else if (MemSize <= MEM_256K) { TrPageSize = PS_256K; } else if (MemSize <= MEM_1M) { TrPageSize = PS_1M; } else if (MemSize <= MEM_4M) { TrPageSize = PS_4M; } else if (MemSize <= MEM_16M) { TrPageSize = PS_16M; } else if (MemSize <= MEM_64M) { TrPageSize = PS_64M; } else if (MemSize <= MEM_256M) { TrPageSize = PS_256M; }
|
|---|
| 538 |
|
|---|
| 539 | #define NUMBER_OF_FWP_ENTRIES 8
|
|---|
| 540 |
|
|---|
| 541 | #define KERNEL_BASE KADDRESS_BASE+0x80000000
|
|---|
| 542 | #define KERNEL_BASE2 KADDRESS_BASE+0x81000000
|
|---|
| 543 |
|
|---|
| 544 | #define PDR_TR_INITIAL TR_VALUE(0,0,2,0,1,1,0,1)
|
|---|
| 545 | #define KIPCR_TR_INITIAL TR_VALUE(0,0,2,0,1,1,0,1)
|
|---|
| 546 | #define USPCR_TR_INITIAL TR_VALUE(0,0,0,3,1,1,0,1)
|
|---|
| 547 |
|
|---|
| 548 | #define PTA_INITIAL 0x001
|
|---|
| 549 |
|
|---|
| 550 | #define DCR_INITIAL 0x0000000000007e05
|
|---|
| 551 |
|
|---|
| 552 | #define PSRL_INITIAL 0x086a2008
|
|---|
| 553 |
|
|---|
| 554 | #define USER_PSR_INITIAL 0x00001013082a6008ll
|
|---|
| 555 |
|
|---|
| 556 | #define USER_FPSR_INITIAL 0x9804C0270033F
|
|---|
| 557 |
|
|---|
| 558 | #define USER_DCR_INITIAL 0x0000000000007f05ll
|
|---|
| 559 |
|
|---|
| 560 | #define USER_RSC_INITIAL ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE) | (0x3<<RSC_PL))
|
|---|
| 561 |
|
|---|
| 562 | #define USER_CODE_DESCRIPTOR 0xCFBFFFFF00000000
|
|---|
| 563 | #define USER_DATA_DESCRIPTOR 0xCF3FFFFF00000000
|
|---|
| 564 |
|
|---|
| 565 | #define STACK_SCRATCH_AREA 16
|
|---|
| 566 |
|
|---|
| 567 | #ifdef _WIN64
|
|---|
| 568 | #define INT_ROUTINES_SHIFT 3
|
|---|
| 569 | #else
|
|---|
| 570 | #define INT_ROUTINES_SHIFT 2
|
|---|
| 571 | #endif
|
|---|
| 572 |
|
|---|
| 573 | #define DISABLE_INTERRUPTS(reg) mov reg = psr; rsm 1 << PSR_I
|
|---|
| 574 |
|
|---|
| 575 | #define RESTORE_INTERRUPTS(reg) tbit##.##nz pt0,pt1 = reg,PSR_I;; ;(pt0) ssm 1 << PSR_I ;(pt1) rsm 1 << PSR_I
|
|---|
| 576 |
|
|---|
| 577 | #define FAST_DISABLE_INTERRUPTS rsm 1 << PSR_I
|
|---|
| 578 |
|
|---|
| 579 | #define FAST_ENABLE_INTERRUPTS ssm 1 << PSR_I
|
|---|
| 580 |
|
|---|
| 581 | #define YIELD hint##.##m 0
|
|---|
| 582 |
|
|---|
| 583 | #define PCR_ENTRY 0
|
|---|
| 584 | #define PDR_ENTRY 2
|
|---|
| 585 | #define LARGE_ENTRY 3
|
|---|
| 586 | #define DMA_ENTRY 4
|
|---|
| 587 |
|
|---|
| 588 | #define TB_ENTRY_SIZE (3 *4)
|
|---|
| 589 | #define FIXED_BASE 0
|
|---|
| 590 | #define FIXED_ENTRIES (DMA_ENTRY + 1)
|
|---|
| 591 |
|
|---|
| 592 | #define DCACHE_SIZE 4 *1024
|
|---|
| 593 | #define ICACHE_SIZE 4 *1024
|
|---|
| 594 | #define MINIMUM_CACHE_SIZE 4 *1024
|
|---|
| 595 | #define MAXIMUM_CACHE_SIZE 128 *1024
|
|---|
| 596 |
|
|---|
| 597 | #define KSEG3_RID 0x00000
|
|---|
| 598 | #define START_GLOBAL_RID 0x00001
|
|---|
| 599 | #define HAL_RID 0x00002
|
|---|
| 600 | #define START_SESSION_RID 0x00003
|
|---|
| 601 | #define START_PROCESS_RID 0x00004
|
|---|
| 602 |
|
|---|
| 603 | #define MAXIMUM_RID 0x3FFFF
|
|---|
| 604 |
|
|---|
| 605 | #define START_SEQUENCE 1
|
|---|
| 606 | #define MAXIMUM_SEQUENCE 0xFFFFFFFFFFFFFFFF
|
|---|
| 607 |
|
|---|
| 608 | #define SBTTL(x)
|
|---|
| 609 |
|
|---|
| 610 | #define PROLOGUE_BEGIN .##prologue;
|
|---|
| 611 | #define PROLOGUE_END .##body;
|
|---|
| 612 |
|
|---|
| 613 | #define ALTERNATE_ENTRY(Name) .##global Name; .##type Name,@function; Name::
|
|---|
| 614 |
|
|---|
| 615 | #define CPUBLIC_LEAF_ENTRY(Name,i) .##text; .##proc Name##@##i; Name##@##i::
|
|---|
| 616 |
|
|---|
| 617 | #define LEAF_ENTRY(Name) .##text; .##global Name; .##proc Name; Name::
|
|---|
| 618 |
|
|---|
| 619 | #define LEAF_SETUP(i,l,o,r) .##regstk i,l,o,r; alloc r31=ar##.##pfs,i,l,o,r
|
|---|
| 620 |
|
|---|
| 621 | #define CPUBLIC_NESTED_ENTRY(Name,i) .##text; .##proc Name##@##i; .##unwentry; Name##@##i::
|
|---|
| 622 |
|
|---|
| 623 | #define NESTED_ENTRY_EX(Name,Handler) .##text; .##global Name; .##proc Name; .##personality Handler; Name::
|
|---|
| 624 |
|
|---|
| 625 | #define NESTED_ENTRY(Name) .##text; .##global Name; .##proc Name; Name::
|
|---|
| 626 |
|
|---|
| 627 | #define NESTED_SETUP(i,l,o,r) .##regstk i,l,o,r; .##prologue 0xC,loc0; alloc savedpfs=ar##.##pfs,i,l,o,r ; mov savedbrp=brp;
|
|---|
| 628 |
|
|---|
| 629 | #define LEAF_RETURN br##.##ret##.##sptk##.##few##.##clr brp
|
|---|
| 630 |
|
|---|
| 631 | #define NESTED_RETURN mov ar##.##pfs = savedpfs; mov brp = savedbrp; br##.##ret##.##sptk##.##few##.##clr brp
|
|---|
| 632 |
|
|---|
| 633 | #define LEAF_EXIT(Name) .##endp Name;
|
|---|
| 634 |
|
|---|
| 635 | #define NESTED_EXIT(Name) .##endp Name;
|
|---|
| 636 |
|
|---|
| 637 | #ifdef _WIN64
|
|---|
| 638 | #define LDPTR(rD,rPtr) ld8 rD = [rPtr]
|
|---|
| 639 | #else
|
|---|
| 640 | #define LDPTR(rD,rPtr) ld4 rD = [rPtr] ; ;; ; sxt4 rD = rD
|
|---|
| 641 | #endif
|
|---|
| 642 |
|
|---|
| 643 | #ifdef _WIN64
|
|---|
| 644 | #define LDPTRINC(rD,rPtr,imm) ld8 rD = [rPtr],imm
|
|---|
| 645 | #else
|
|---|
| 646 | #define LDPTRINC(rD,rPtr,imm) ld4 rD = [rPtr],imm ; ;; ; sxt4 rD = rD
|
|---|
| 647 | #endif
|
|---|
| 648 |
|
|---|
| 649 | #ifdef _WIN64
|
|---|
| 650 | #define PLDPTRINC(rP,rD,rPtr,imm) (rP) ld8 rD = [rPtr],imm
|
|---|
| 651 | #else
|
|---|
| 652 | #define PLDPTRINC(rP,rD,rPtr,imm) (rP) ld4 rD = [rPtr],imm ; ;; ;(rP) sxt4 rD = rD
|
|---|
| 653 | #endif
|
|---|
| 654 |
|
|---|
| 655 | #ifdef _WIN64
|
|---|
| 656 | #define PLDPTR(rP,rD,rPtr) (rP) ld8 rD = [rPtr]
|
|---|
| 657 | #else
|
|---|
| 658 | #define PLDPTR(rP,rD,rPtr) (rP) ld4 rD = [rPtr] ; ;; ;(rP) sxt4 rD = rD
|
|---|
| 659 | #endif
|
|---|
| 660 |
|
|---|
| 661 | #ifdef _WIN64
|
|---|
| 662 | #define STPTR(rPtr,rS) st8 [rPtr] = rS
|
|---|
| 663 | #else
|
|---|
| 664 | #define STPTR(rPtr,rS) st4 [rPtr] = rS
|
|---|
| 665 | #endif
|
|---|
| 666 |
|
|---|
| 667 | #ifdef _WIN64
|
|---|
| 668 | #define PSTPTR(rP,rPtr,rS) (rP) st8 [rPtr] = rS
|
|---|
| 669 | #else
|
|---|
| 670 | #define PSTPTR(rP,rPtr,rS) (rP) st4 [rPtr] = rS
|
|---|
| 671 | #endif
|
|---|
| 672 |
|
|---|
| 673 | #ifdef _WIN64
|
|---|
| 674 | #define STPTRINC(rPtr,rS,imm) st8 [rPtr] = rS,imm
|
|---|
| 675 | #else
|
|---|
| 676 | #define STPTRINC(rPtr,rS,imm) st4 [rPtr] = rS,imm
|
|---|
| 677 | #endif
|
|---|
| 678 |
|
|---|
| 679 | #ifdef _WIN64
|
|---|
| 680 | #define ARGPTR(rPtr)
|
|---|
| 681 | #else
|
|---|
| 682 | #define ARGPTR(rPtr) sxt4 rPtr = rPtr
|
|---|
| 683 | #endif
|
|---|
| 684 |
|
|---|
| 685 | #define ACQUIRE_SPINLOCK(rpLock,rOwn,Loop) cmp##.##eq pt0,pt1 = zero,zero ; ;; ;Loop: ;.pred.rel "mutex",pt0,pt1 ;(pt1) YIELD ;(pt0) xchg8 t22 = [rpLock],rOwn ;(pt1) ld8##.##nt1 t22 = [rpLock] ; ;; ;(pt0) cmp##.##ne pt2 = zero,t22 ; cmp##.##eq pt0,pt1 = zero,t22 ;(pt2) br##.##dpnt Loop
|
|---|
| 686 |
|
|---|
| 687 | #define RELEASE_SPINLOCK(rpLock) st8##.##rel [rpLock] = zero
|
|---|
| 688 |
|
|---|
| 689 | #define PRELEASE_SPINLOCK(px,rpLock) (px) st8##.##rel [rpLock] = zero
|
|---|
| 690 |
|
|---|
| 691 | #define END_OF_INTERRUPT mov cr##.##eoi = zero ; ;; ; srlz##.##d
|
|---|
| 692 |
|
|---|
| 693 | #ifndef SHADOW_IRQL_IMPLEMENTATION
|
|---|
| 694 | #define GET_IRQL(rOldIrql) mov rOldIrql = cr##.##tpr ;; extr##.##u rOldIrql = rOldIrql,TPR_MIC,TPR_MIC_LEN
|
|---|
| 695 | #else
|
|---|
| 696 | #define GET_IRQL(rOldIrql) movl rOldIrql = KiPcr+PcCurrentIrql;; ld1 rOldIrql = [rOldIrql]
|
|---|
| 697 | #endif
|
|---|
| 698 |
|
|---|
| 699 | #ifndef SHADOW_IRQL_IMPLEMENTATION
|
|---|
| 700 | #define SET_IRQL(rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; mov cr##.##tpr = t22;; ; srlz##.##d
|
|---|
| 701 | #else
|
|---|
| 702 | #define SET_IRQL(rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; movl t21 = KiPcr+PcCurrentIrql;; ; mov cr##.##tpr = t22 ; st1 [t21] = rNewIrql
|
|---|
| 703 | #endif
|
|---|
| 704 |
|
|---|
| 705 | #ifndef SHADOW_IRQL_IMPLEMENTATION
|
|---|
| 706 | #define PSET_IRQL(pr,rNewIrql) dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ;(pr) mov cr##.##tpr = t22;; ;(pr) srlz##.##d
|
|---|
| 707 | #else
|
|---|
| 708 | #define PSET_IRQL(pr,rNewIrql) mov t21 = rNewIrql ; dep##.##z t22 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ;(pr) mov cr##.##tpr = t22 ;(pr) movl t22 = KiPcr+PcCurrentIrql;; ;(pr) st1 [t22] = t21
|
|---|
| 709 | #endif
|
|---|
| 710 |
|
|---|
| 711 | #define SWAP_IRQL(rNewIrql) movl t22 = KiPcr+PcCurrentIrql;; ; ld1 v0 = [t22] ; dep##.##z t21 = rNewIrql,TPR_MIC,TPR_MIC_LEN;; ; mov cr##.##tpr = t21 ; st1 [t22] = rNewIrql
|
|---|
| 712 | #define GET_IRQL_FOR_VECTOR(pGet,rIrql,rVector) (pGet) shr rIrql = rVector,VECTOR_IRQL_SHIFT
|
|---|
| 713 | #define GET_VECTOR_FOR_IRQL(pGet,rVector,rIrql) (pGet) shl rVector = rIrql,VECTOR_IRQL_SHIFT
|
|---|
| 714 | #define REQUEST_APC_INT(pReq) mov t20 = 1 ; movl t21 = KiPcr+PcApcInterrupt ; ;; ;(pReq) st1 [t21] = t20
|
|---|
| 715 | #define REQUEST_DISPATCH_INT(pReq) mov t20 = 1 ; movl t21 = KiPcr+PcDispatchInterrupt ; ;; ;(pReq) st1 [t21] = t20
|
|---|
| 716 |
|
|---|
| 717 | #define beginSection(SectName) .##section .CRT$##SectName,"a","progbits"
|
|---|
| 718 | #define endSection(SectName)
|
|---|
| 719 |
|
|---|
| 720 | #define PublicFunction(Name) .##global Name; .##type Name,@function
|
|---|
