| 1 | /**
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| 2 | * This file is part of the mingw-w64 runtime package.
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| 3 | * No warranty is given; refer to the file DISCLAIMER within this package.
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| 4 | */
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| 5 |
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| 6 | #ifndef _PCIPROP_
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| 7 | #define _PCIPROP_
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| 8 |
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| 9 | #include <winapifamily.h>
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| 10 | #include <devpropdef.h>
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| 11 |
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| 12 | #if WINAPI_FAMILY_PARTITION (WINAPI_PARTITION_DESKTOP)
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| 13 |
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| 14 | #define DEFINE_PCI_ROOT_BUS_DEVPKEY(_DPKNAME, _PID) DEFINE_DEVPROPKEY ((_DPKNAME), 0xd817fc28, 0x793e, 0x4b9e, 0x99, 0x70, 0x46, 0x9d, 0x8b, 0xe6, 0x30, 0x73, (_PID))
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| 15 | #define DEFINE_PCI_DEVICE_DEVPKEY(_DPKNAME, _PID) DEFINE_DEVPROPKEY ((_DPKNAME), 0x3ab22e31, 0x8264, 0x4b4e, 0x9a, 0xf5, 0xa8, 0xd2, 0xd8, 0xe3, 0x3e, 0x62, (_PID))
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| 16 |
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| 17 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SecondaryInterface, 1);
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| 18 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_CurrentSpeedAndMode, 2);
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| 19 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SupportedSpeedsAndModes, 3);
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| 20 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_DeviceIDMessagingCapable, 4);
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| 21 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SecondaryBusWidth, 5);
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| 22 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ExtendedConfigAvailable, 6);
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| 23 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ExtendedPCIConfigOpRegionSupport, 7);
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| 24 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ASPMSupport, 8);
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| 25 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ClockPowerManagementSupport, 9);
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| 26 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCISegmentGroupsSupport, 10);
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| 27 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_MSISupport, 11);
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| 28 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressNativeHotPlugControl, 12);
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| 29 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SHPCNativeHotPlugControl, 13);
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| 30 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressNativePMEControl, 14);
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| 31 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressAERControl, 15);
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| 32 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressCapabilityControl, 16);
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| 33 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_NativePciExpressControl, 17);
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| 34 | DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SystemMsiSupport, 18);
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| 35 |
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| 36 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_DeviceType, 1);
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| 37 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentSpeedAndMode, 2);
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| 38 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_BaseClass, 3);
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| 39 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_SubClass, 4);
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| 40 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ProgIf, 5);
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| 41 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentPayloadSize, 6);
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| 42 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxPayloadSize, 7);
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| 43 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxReadRequestSize, 8);
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| 44 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentLinkSpeed, 9);
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| 45 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentLinkWidth, 10);
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| 46 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxLinkSpeed, 11);
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| 47 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxLinkWidth, 12);
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| 48 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ExpressSpecVersion, 13);
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| 49 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_InterruptSupport, 14);
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| 50 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_InterruptMessageMaximum, 15);
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| 51 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_BarTypes, 16);
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| 52 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AERCapabilityPresent, 17);
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| 53 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_FirmwareErrorHandling, 18);
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| 54 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Uncorrectable_Error_Mask, 19);
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| 55 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Uncorrectable_Error_Severity, 20);
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| 56 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Correctable_Error_Mask, 21);
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| 57 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ECRC_Errors, 22);
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| 58 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Error_Reporting, 23);
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| 59 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_RootError_Reporting, 24);
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| 60 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_S0WakeupSupported, 25);
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| 61 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_SriovSupport, 26);
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| 62 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Label_Id, 27);
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| 63 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Label_String, 28);
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| 64 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AcsSupport, 29);
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| 65 | DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AriSupport, 30);
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| 66 |
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| 67 | #define DevProp_PciRootBus_SecondaryInterface_PciConventional 0
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| 68 | #define DevProp_PciRootBus_SecondaryInterface_PciXMode1 1
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| 69 | #define DevProp_PciRootBus_SecondaryInterface_PciXMode2 2
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| 70 | #define DevProp_PciRootBus_SecondaryInterface_PciExpress 3
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| 71 |
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| 72 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_33Mhz 0
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| 73 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_66Mhz 1
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| 74 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_66Mhz 2
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| 75 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_100Mhz 3
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| 76 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_133Mhz 4
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| 77 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_66Mhz 5
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| 78 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_100Mhz 6
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| 79 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_133Mhz 7
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| 80 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_66Mhz 8
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| 81 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_100Mhz 9
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| 82 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_133Mhz 10
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| 83 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_66Mhz 11
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| 84 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_100Mhz 12
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| 85 | #define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_133Mhz 13
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| 86 |
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| 87 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_33Mhz 1
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| 88 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_66Mhz 2
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| 89 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_66Mhz 4
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| 90 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_133Mhz 8
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| 91 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_266Mhz 16
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| 92 | #define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_533Mhz 32
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| 93 |
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| 94 | #define DevProp_PciRootBus_BusWidth_32Bits 0
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| 95 | #define DevProp_PciRootBus_BusWidth_64Bits 1
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| 96 |
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| 97 | #define DevProp_PciDevice_DeviceType_PciConventional 0
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| 98 | #define DevProp_PciDevice_DeviceType_PciX 1
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| 99 | #define DevProp_PciDevice_DeviceType_PciExpressEndpoint 2
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| 100 | #define DevProp_PciDevice_DeviceType_PciExpressLegacyEndpoint 3
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| 101 | #define DevProp_PciDevice_DeviceType_PciExpressRootComplexIntegratedEndpoint 4
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| 102 | #define DevProp_PciDevice_DeviceType_PciExpressTreatedAsPci 5
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| 103 | #define DevProp_PciDevice_BridgeType_PciConventional 6
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| 104 | #define DevProp_PciDevice_BridgeType_PciX 7
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| 105 | #define DevProp_PciDevice_BridgeType_PciExpressRootPort 8
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| 106 | #define DevProp_PciDevice_BridgeType_PciExpressUpstreamSwitchPort 9
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| 107 | #define DevProp_PciDevice_BridgeType_PciExpressDownstreamSwitchPort 10
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| 108 | #define DevProp_PciDevice_BridgeType_PciExpressToPciXBridge 11
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| 109 | #define DevProp_PciDevice_BridgeType_PciXToExpressBridge 12
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| 110 | #define DevProp_PciDevice_BridgeType_PciExpressTreatedAsPci 13
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| 111 |
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| 112 | #define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_33MHz 0
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| 113 | #define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_66MHz 1
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| 114 |
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| 115 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode_Conventional_Pci 0x0
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| 116 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_66Mhz 0x1
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| 117 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_100Mhz 0x2
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| 118 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_133MHZ 0x3
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| 119 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_66Mhz 0x5
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| 120 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_100Mhz 0x6
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| 121 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_133Mhz 0x7
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| 122 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_66MHz 0x9
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| 123 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_100MHz 0xa
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| 124 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_133MHz 0xb
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| 125 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_66MHz 0xd
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| 126 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_100MHz 0xe
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| 127 | #define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_133MHz 0xf
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| 128 |
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| 129 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_128Bytes 0
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| 130 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_256Bytes 1
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| 131 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_512Bytes 2
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| 132 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_1024Bytes 3
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| 133 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_2048Bytes 4
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| 134 | #define DevProp_PciExpressDevice_PayloadOrRequestSize_4096Bytes 5
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| 135 |
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| 136 | #define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
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| 137 | #define DevProp_PciExpressDevice_LinkSpeed_Five_Gbps 2
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| 138 |
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| 139 | #define DevProp_PciExpressDevice_LinkWidth_By_1 1
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| 140 | #define DevProp_PciExpressDevice_LinkWidth_By_2 2
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| 141 | #define DevProp_PciExpressDevice_LinkWidth_By_4 4
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| 142 | #define DevProp_PciExpressDevice_LinkWidth_By_8 8
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| 143 | #define DevProp_PciExpressDevice_LinkWidth_By_12 12
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| 144 | #define DevProp_PciExpressDevice_LinkWidth_By_16 16
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| 145 | #define DevProp_PciExpressDevice_LinkWidth_By_32 32
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| 146 |
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| 147 | #define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
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| 148 |
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| 149 | #define DevProp_PciExpressDevice_Spec_Version_10 1
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| 150 | #define DevProp_PciExpressDevice_Spec_Version_11 2
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| 151 |
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| 152 | #define DevProp_PciDevice_InterruptType_LineBased 1
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| 153 | #define DevProp_PciDevice_InterruptType_Msi 2
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| 154 | #define DevProp_PciDevice_InterruptType_MsiX 4
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| 155 |
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| 156 | #define DevProp_PciDevice_IoBarCount(_PD) ((_PD) & 0xff)
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| 157 | #define DevProp_PciDevice_NonPrefetchable_MemoryBarCount(_PD) (((_PD) >> 8) & 0xff)
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| 158 | #define DevProp_PciDevice_32BitPrefetchable_MemoryBarCount(_PD) (((_PD) >> 16) & 0xff)
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| 159 | #define DevProp_PciDevice_64BitPrefetchable_MemoryBarCount(_PD) (((_PD) >> 24) & 0xff)
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| 160 |
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| 161 | #define DevProp_PciDevice_SriovSupport_Ok 0x0
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| 162 | #define DevProp_PciDevice_SriovSupport_MissingAcs 0x1
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| 163 | #define DevProp_PciDevice_SriovSupport_MissingPfDriver 0x2
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| 164 | #define DevProp_PciDevice_SriovSupport_NoBusResource 0x3
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| 165 | #define DevProp_PciDevice_SriovSupport_DidntGetVfBarSpace 0x4
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| 166 |
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| 167 | #define DevProp_PciDevice_AcsSupport_Present 0x0
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| 168 | #define DevProp_PciDevice_AcsSupport_NotNeeded 0x1
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| 169 | #define DevProp_PciDevice_AcsSupport_Missing 0x2
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| 170 |
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| 171 | #endif
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| 172 | #endif
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