source: Daodan/MSYS2/mingw32/i686-w64-mingw32/include/pciprop.h@ 1167

Last change on this file since 1167 was 1166, checked in by rossy, 3 years ago

Daodan: Replace MinGW build env with an up-to-date MSYS2 env
File size: 9.4 KB
Line 
1/**
2 * This file is part of the mingw-w64 runtime package.
3 * No warranty is given; refer to the file DISCLAIMER within this package.
4 */
5
6#ifndef _PCIPROP_
7#define _PCIPROP_
8
9#include <winapifamily.h>
10#include <devpropdef.h>
11
12#if WINAPI_FAMILY_PARTITION (WINAPI_PARTITION_DESKTOP)
13
14#define DEFINE_PCI_ROOT_BUS_DEVPKEY(_DPKNAME, _PID) DEFINE_DEVPROPKEY ((_DPKNAME), 0xd817fc28, 0x793e, 0x4b9e, 0x99, 0x70, 0x46, 0x9d, 0x8b, 0xe6, 0x30, 0x73, (_PID))
15#define DEFINE_PCI_DEVICE_DEVPKEY(_DPKNAME, _PID) DEFINE_DEVPROPKEY ((_DPKNAME), 0x3ab22e31, 0x8264, 0x4b4e, 0x9a, 0xf5, 0xa8, 0xd2, 0xd8, 0xe3, 0x3e, 0x62, (_PID))
16
17DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SecondaryInterface, 1);
18DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_CurrentSpeedAndMode, 2);
19DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SupportedSpeedsAndModes, 3);
20DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_DeviceIDMessagingCapable, 4);
21DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SecondaryBusWidth, 5);
22DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ExtendedConfigAvailable, 6);
23DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ExtendedPCIConfigOpRegionSupport, 7);
24DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ASPMSupport, 8);
25DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_ClockPowerManagementSupport, 9);
26DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCISegmentGroupsSupport, 10);
27DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_MSISupport, 11);
28DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressNativeHotPlugControl, 12);
29DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SHPCNativeHotPlugControl, 13);
30DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressNativePMEControl, 14);
31DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressAERControl, 15);
32DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_PCIExpressCapabilityControl, 16);
33DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_NativePciExpressControl, 17);
34DEFINE_PCI_ROOT_BUS_DEVPKEY (DEVPKEY_PciRootBus_SystemMsiSupport, 18);
35
36DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_DeviceType, 1);
37DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentSpeedAndMode, 2);
38DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_BaseClass, 3);
39DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_SubClass, 4);
40DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ProgIf, 5);
41DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentPayloadSize, 6);
42DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxPayloadSize, 7);
43DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxReadRequestSize, 8);
44DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentLinkSpeed, 9);
45DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_CurrentLinkWidth, 10);
46DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxLinkSpeed, 11);
47DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_MaxLinkWidth, 12);
48DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ExpressSpecVersion, 13);
49DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_InterruptSupport, 14);
50DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_InterruptMessageMaximum, 15);
51DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_BarTypes, 16);
52DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AERCapabilityPresent, 17);
53DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_FirmwareErrorHandling, 18);
54DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Uncorrectable_Error_Mask, 19);
55DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Uncorrectable_Error_Severity, 20);
56DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Correctable_Error_Mask, 21);
57DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_ECRC_Errors, 22);
58DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Error_Reporting, 23);
59DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_RootError_Reporting, 24);
60DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_S0WakeupSupported, 25);
61DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_SriovSupport, 26);
62DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Label_Id, 27);
63DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_Label_String, 28);
64DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AcsSupport, 29);
65DEFINE_PCI_DEVICE_DEVPKEY (DEVPKEY_PciDevice_AriSupport, 30);
66
67#define DevProp_PciRootBus_SecondaryInterface_PciConventional 0
68#define DevProp_PciRootBus_SecondaryInterface_PciXMode1 1
69#define DevProp_PciRootBus_SecondaryInterface_PciXMode2 2
70#define DevProp_PciRootBus_SecondaryInterface_PciExpress 3
71
72#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_33Mhz 0
73#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_66Mhz 1
74#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_66Mhz 2
75#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_100Mhz 3
76#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_133Mhz 4
77#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_66Mhz 5
78#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_100Mhz 6
79#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_133Mhz 7
80#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_66Mhz 8
81#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_100Mhz 9
82#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_133Mhz 10
83#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_66Mhz 11
84#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_100Mhz 12
85#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_133Mhz 13
86
87#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_33Mhz 1
88#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_66Mhz 2
89#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_66Mhz 4
90#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_133Mhz 8
91#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_266Mhz 16
92#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_533Mhz 32
93
94#define DevProp_PciRootBus_BusWidth_32Bits 0
95#define DevProp_PciRootBus_BusWidth_64Bits 1
96
97#define DevProp_PciDevice_DeviceType_PciConventional 0
98#define DevProp_PciDevice_DeviceType_PciX 1
99#define DevProp_PciDevice_DeviceType_PciExpressEndpoint 2
100#define DevProp_PciDevice_DeviceType_PciExpressLegacyEndpoint 3
101#define DevProp_PciDevice_DeviceType_PciExpressRootComplexIntegratedEndpoint 4
102#define DevProp_PciDevice_DeviceType_PciExpressTreatedAsPci 5
103#define DevProp_PciDevice_BridgeType_PciConventional 6
104#define DevProp_PciDevice_BridgeType_PciX 7
105#define DevProp_PciDevice_BridgeType_PciExpressRootPort 8
106#define DevProp_PciDevice_BridgeType_PciExpressUpstreamSwitchPort 9
107#define DevProp_PciDevice_BridgeType_PciExpressDownstreamSwitchPort 10
108#define DevProp_PciDevice_BridgeType_PciExpressToPciXBridge 11
109#define DevProp_PciDevice_BridgeType_PciXToExpressBridge 12
110#define DevProp_PciDevice_BridgeType_PciExpressTreatedAsPci 13
111
112#define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_33MHz 0
113#define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_66MHz 1
114
115#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode_Conventional_Pci 0x0
116#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_66Mhz 0x1
117#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_100Mhz 0x2
118#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_133MHZ 0x3
119#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_66Mhz 0x5
120#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_100Mhz 0x6
121#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_133Mhz 0x7
122#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_66MHz 0x9
123#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_100MHz 0xa
124#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_133MHz 0xb
125#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_66MHz 0xd
126#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_100MHz 0xe
127#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_133MHz 0xf
128
129#define DevProp_PciExpressDevice_PayloadOrRequestSize_128Bytes 0
130#define DevProp_PciExpressDevice_PayloadOrRequestSize_256Bytes 1
131#define DevProp_PciExpressDevice_PayloadOrRequestSize_512Bytes 2
132#define DevProp_PciExpressDevice_PayloadOrRequestSize_1024Bytes 3
133#define DevProp_PciExpressDevice_PayloadOrRequestSize_2048Bytes 4
134#define DevProp_PciExpressDevice_PayloadOrRequestSize_4096Bytes 5
135
136#define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
137#define DevProp_PciExpressDevice_LinkSpeed_Five_Gbps 2
138
139#define DevProp_PciExpressDevice_LinkWidth_By_1 1
140#define DevProp_PciExpressDevice_LinkWidth_By_2 2
141#define DevProp_PciExpressDevice_LinkWidth_By_4 4
142#define DevProp_PciExpressDevice_LinkWidth_By_8 8
143#define DevProp_PciExpressDevice_LinkWidth_By_12 12
144#define DevProp_PciExpressDevice_LinkWidth_By_16 16
145#define DevProp_PciExpressDevice_LinkWidth_By_32 32
146
147#define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
148
149#define DevProp_PciExpressDevice_Spec_Version_10 1
150#define DevProp_PciExpressDevice_Spec_Version_11 2
151
152#define DevProp_PciDevice_InterruptType_LineBased 1
153#define DevProp_PciDevice_InterruptType_Msi 2
154#define DevProp_PciDevice_InterruptType_MsiX 4
155
156#define DevProp_PciDevice_IoBarCount(_PD) ((_PD) & 0xff)
157#define DevProp_PciDevice_NonPrefetchable_MemoryBarCount(_PD) (((_PD) >> 8) & 0xff)
158#define DevProp_PciDevice_32BitPrefetchable_MemoryBarCount(_PD) (((_PD) >> 16) & 0xff)
159#define DevProp_PciDevice_64BitPrefetchable_MemoryBarCount(_PD) (((_PD) >> 24) & 0xff)
160
161#define DevProp_PciDevice_SriovSupport_Ok 0x0
162#define DevProp_PciDevice_SriovSupport_MissingAcs 0x1
163#define DevProp_PciDevice_SriovSupport_MissingPfDriver 0x2
164#define DevProp_PciDevice_SriovSupport_NoBusResource 0x3
165#define DevProp_PciDevice_SriovSupport_DidntGetVfBarSpace 0x4
166
167#define DevProp_PciDevice_AcsSupport_Present 0x0
168#define DevProp_PciDevice_AcsSupport_NotNeeded 0x1
169#define DevProp_PciDevice_AcsSupport_Missing 0x2
170
171#endif
172#endif
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