source: Daodan/MSYS2/mingw32/i686-w64-mingw32/include/winhvplatformdefs.h@ 1181

Last change on this file since 1181 was 1166, checked in by rossy, 3 years ago

Daodan: Replace MinGW build env with an up-to-date MSYS2 env
File size: 54.2 KB
Line 
1/**
2 * This file is part of the mingw-w64 runtime package.
3 * No warranty is given; refer to the file DISCLAIMER within this package.
4 */
5
6#ifndef _WINHVAPIDEFS_H_
7#define _WINHVAPIDEFS_H_
8
9typedef enum WHV_CAPABILITY_CODE {
10 WHvCapabilityCodeHypervisorPresent = 0x00000000,
11 WHvCapabilityCodeFeatures = 0x00000001,
12 WHvCapabilityCodeExtendedVmExits = 0x00000002,
13 WHvCapabilityCodeExceptionExitBitmap = 0x00000003,
14 WHvCapabilityCodeX64MsrExitBitmap = 0x00000004,
15 WHvCapabilityCodeGpaRangePopulateFlags = 0x00000005,
16 WHvCapabilityCodeSchedulerFeatures = 0x00000006,
17 WHvCapabilityCodeProcessorVendor = 0x00001000,
18 WHvCapabilityCodeProcessorFeatures = 0x00001001,
19 WHvCapabilityCodeProcessorClFlushSize = 0x00001002,
20 WHvCapabilityCodeProcessorXsaveFeatures = 0x00001003,
21 WHvCapabilityCodeProcessorClockFrequency = 0x00001004,
22 WHvCapabilityCodeInterruptClockFrequency = 0x00001005,
23 WHvCapabilityCodeProcessorFeaturesBanks = 0x00001006,
24 WHvCapabilityCodeProcessorFrequencyCap = 0x00001007,
25 WHvCapabilityCodeSyntheticProcessorFeaturesBanks = 0x00001008,
26 WHvCapabilityCodeProcessorPerfmonFeatures = 0x00001009
27} WHV_CAPABILITY_CODE;
28
29typedef union WHV_CAPABILITY_FEATURES {
30 __C89_NAMELESS struct {
31 UINT64 PartialUnmap : 1;
32 UINT64 LocalApicEmulation : 1;
33 UINT64 Xsave : 1;
34 UINT64 DirtyPageTracking : 1;
35 UINT64 SpeculationControl : 1;
36 UINT64 ApicRemoteRead : 1;
37 UINT64 IdleSuspend : 1;
38 UINT64 VirtualPciDeviceSupport : 1;
39 UINT64 IommuSupport : 1;
40 UINT64 VpHotAddRemove : 1;
41 UINT64 Reserved : 54;
42 };
43 UINT64 AsUINT64;
44} WHV_CAPABILITY_FEATURES;
45
46C_ASSERT(sizeof(WHV_CAPABILITY_FEATURES) == sizeof(UINT64));
47
48typedef union WHV_EXTENDED_VM_EXITS {
49 __C89_NAMELESS struct {
50 UINT64 X64CpuidExit : 1;
51 UINT64 X64MsrExit : 1;
52 UINT64 ExceptionExit : 1;
53 UINT64 X64RdtscExit : 1;
54 UINT64 X64ApicSmiExitTrap : 1;
55 UINT64 HypercallExit : 1;
56 UINT64 X64ApicInitSipiExitTrap : 1;
57 UINT64 X64ApicWriteLint0ExitTrap : 1;
58 UINT64 X64ApicWriteLint1ExitTrap : 1;
59 UINT64 X64ApicWriteSvrExitTrap : 1;
60 UINT64 UnknownSynicConnection : 1;
61 UINT64 RetargetUnknownVpciDevice : 1;
62 UINT64 X64ApicWriteLdrExitTrap : 1;
63 UINT64 X64ApicWriteDfrExitTrap : 1;
64 UINT64 GpaAccessFaultExit : 1;
65 UINT64 Reserved : 49;
66 };
67 UINT64 AsUINT64;
68} WHV_EXTENDED_VM_EXITS;
69
70C_ASSERT(sizeof(WHV_EXTENDED_VM_EXITS) == sizeof(UINT64));
71
72typedef enum WHV_PROCESSOR_VENDOR {
73 WHvProcessorVendorAmd = 0x0000,
74 WHvProcessorVendorIntel = 0x0001,
75 WHvProcessorVendorHygon = 0x0002
76} WHV_PROCESSOR_VENDOR;
77
78typedef union WHV_PROCESSOR_FEATURES {
79 __C89_NAMELESS struct {
80 UINT64 Sse3Support : 1;
81 UINT64 LahfSahfSupport : 1;
82 UINT64 Ssse3Support : 1;
83 UINT64 Sse4_1Support : 1;
84 UINT64 Sse4_2Support : 1;
85 UINT64 Sse4aSupport : 1;
86 UINT64 XopSupport : 1;
87 UINT64 PopCntSupport : 1;
88 UINT64 Cmpxchg16bSupport : 1;
89 UINT64 Altmovcr8Support : 1;
90 UINT64 LzcntSupport : 1;
91 UINT64 MisAlignSseSupport : 1;
92 UINT64 MmxExtSupport : 1;
93 UINT64 Amd3DNowSupport : 1;
94 UINT64 ExtendedAmd3DNowSupport : 1;
95 UINT64 Page1GbSupport : 1;
96 UINT64 AesSupport : 1;
97 UINT64 PclmulqdqSupport : 1;
98 UINT64 PcidSupport : 1;
99 UINT64 Fma4Support : 1;
100 UINT64 F16CSupport : 1;
101 UINT64 RdRandSupport : 1;
102 UINT64 RdWrFsGsSupport : 1;
103 UINT64 SmepSupport : 1;
104 UINT64 EnhancedFastStringSupport : 1;
105 UINT64 Bmi1Support : 1;
106 UINT64 Bmi2Support : 1;
107 UINT64 Reserved1 : 2;
108 UINT64 MovbeSupport : 1;
109 UINT64 Npiep1Support : 1;
110 UINT64 DepX87FPUSaveSupport : 1;
111 UINT64 RdSeedSupport : 1;
112 UINT64 AdxSupport : 1;
113 UINT64 IntelPrefetchSupport : 1;
114 UINT64 SmapSupport : 1;
115 UINT64 HleSupport : 1;
116 UINT64 RtmSupport : 1;
117 UINT64 RdtscpSupport : 1;
118 UINT64 ClflushoptSupport : 1;
119 UINT64 ClwbSupport : 1;
120 UINT64 ShaSupport : 1;
121 UINT64 X87PointersSavedSupport : 1;
122 UINT64 InvpcidSupport : 1;
123 UINT64 IbrsSupport : 1;
124 UINT64 StibpSupport : 1;
125 UINT64 IbpbSupport : 1;
126 UINT64 Reserved2 : 1;
127 UINT64 SsbdSupport : 1;
128 UINT64 FastShortRepMovSupport : 1;
129 UINT64 Reserved3 : 1;
130 UINT64 RdclNo : 1;
131 UINT64 IbrsAllSupport : 1;
132 UINT64 Reserved4 : 1;
133 UINT64 SsbNo : 1;
134 UINT64 RsbANo : 1;
135 UINT64 Reserved5 : 1;
136 UINT64 RdPidSupport : 1;
137 UINT64 UmipSupport : 1;
138 UINT64 MdsNoSupport : 1;
139 UINT64 MdClearSupport : 1;
140 UINT64 TaaNoSupport : 1;
141 UINT64 TsxCtrlSupport : 1;
142 UINT64 Reserved6 : 1;
143 };
144 UINT64 AsUINT64;
145} WHV_PROCESSOR_FEATURES;
146
147C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES) == sizeof(UINT64));
148
149typedef union WHV_PROCESSOR_FEATURES1 {
150 __C89_NAMELESS struct {
151 UINT64 ACountMCountSupport : 1;
152 UINT64 TscInvariantSupport : 1;
153 UINT64 ClZeroSupport : 1;
154 UINT64 RdpruSupport : 1;
155 UINT64 Reserved2 : 2;
156 UINT64 NestedVirtSupport : 1;
157 UINT64 PsfdSupport: 1;
158 UINT64 CetSsSupport : 1;
159 UINT64 CetIbtSupport : 1;
160 UINT64 VmxExceptionInjectSupport : 1;
161 UINT64 Reserved4 : 1;
162 UINT64 UmwaitTpauseSupport : 1;
163 UINT64 MovdiriSupport : 1;
164 UINT64 Movdir64bSupport : 1;
165 UINT64 CldemoteSupport : 1;
166 UINT64 SerializeSupport : 1;
167 UINT64 TscDeadlineTmrSupport : 1;
168 UINT64 TscAdjustSupport : 1;
169 UINT64 FZLRepMovsb : 1;
170 UINT64 FSRepStosb : 1;
171 UINT64 FSRepCmpsb : 1;
172 UINT64 Reserved5 : 42;
173 };
174 UINT64 AsUINT64;
175} WHV_PROCESSOR_FEATURES1;
176
177C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES1) == sizeof(UINT64));
178
179#define WHV_PROCESSOR_FEATURES_BANKS_COUNT 2
180
181typedef struct WHV_PROCESSOR_FEATURES_BANKS {
182 UINT32 BanksCount;
183 UINT32 Reserved0;
184 __C89_NAMELESS union {
185 __C89_NAMELESS struct {
186 WHV_PROCESSOR_FEATURES Bank0;
187 WHV_PROCESSOR_FEATURES1 Bank1;
188 };
189 UINT64 AsUINT64[WHV_PROCESSOR_FEATURES_BANKS_COUNT];
190 };
191} WHV_PROCESSOR_FEATURES_BANKS;
192
193C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES_BANKS) == sizeof(UINT64) * (WHV_PROCESSOR_FEATURES_BANKS_COUNT + 1));
194
195typedef union WHV_SYNTHETIC_PROCESSOR_FEATURES {
196 __C89_NAMELESS struct {
197 UINT64 HypervisorPresent:1;
198 UINT64 Hv1:1;
199 UINT64 AccessVpRunTimeReg:1;
200 UINT64 AccessPartitionReferenceCounter:1;
201 UINT64 AccessSynicRegs:1;
202 UINT64 AccessSyntheticTimerRegs:1;
203#ifdef __x86_64__
204 UINT64 AccessIntrCtrlRegs:1;
205#else
206 UINT64 ReservedZ6:1;
207#endif
208 UINT64 AccessHypercallRegs:1;
209 UINT64 AccessVpIndex:1;
210 UINT64 AccessPartitionReferenceTsc:1;
211#ifdef __x86_64__
212 UINT64 AccessGuestIdleReg:1;
213 UINT64 AccessFrequencyRegs:1;
214#else
215 UINT64 ReservedZ10:1;
216 UINT64 ReservedZ11:1;
217#endif
218 UINT64 ReservedZ12:1;
219 UINT64 ReservedZ13:1;
220 UINT64 ReservedZ14:1;
221#ifdef __x86_64__
222 UINT64 EnableExtendedGvaRangesForFlushVirtualAddressList:1;
223#else
224 UINT64 ReservedZ15:1;
225#endif
226 UINT64 ReservedZ16:1;
227 UINT64 ReservedZ17:1;
228 UINT64 FastHypercallOutput:1;
229 UINT64 ReservedZ19:1;
230 UINT64 ReservedZ20:1;
231 UINT64 ReservedZ21:1;
232 UINT64 DirectSyntheticTimers:1;
233 UINT64 ReservedZ23:1;
234 UINT64 ExtendedProcessorMasks:1;
235#ifdef __x86_64__
236 UINT64 TbFlushHypercalls:1;
237#else
238 UINT64 ReservedZ25:1;
239#endif
240 UINT64 SyntheticClusterIpi:1;
241 UINT64 NotifyLongSpinWait:1;
242 UINT64 QueryNumaDistance:1;
243 UINT64 SignalEvents:1;
244 UINT64 RetargetDeviceInterrupt:1;
245 UINT64 Reserved:33;
246 };
247 UINT64 AsUINT64;
248} WHV_SYNTHETIC_PROCESSOR_FEATURES;
249
250C_ASSERT(sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES) == 8);
251
252#define WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS_COUNT 1
253
254typedef struct WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS {
255 UINT32 BanksCount;
256 UINT32 Reserved0;
257 __C89_NAMELESS union {
258 __C89_NAMELESS struct {
259 WHV_SYNTHETIC_PROCESSOR_FEATURES Bank0;
260 };
261 UINT64 AsUINT64[WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS_COUNT];
262 };
263} WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS;
264
265C_ASSERT(sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS) == 16);
266
267typedef union _WHV_PROCESSOR_XSAVE_FEATURES {
268 __C89_NAMELESS struct {
269 UINT64 XsaveSupport : 1;
270 UINT64 XsaveoptSupport : 1;
271 UINT64 AvxSupport : 1;
272 UINT64 Avx2Support : 1;
273 UINT64 FmaSupport : 1;
274 UINT64 MpxSupport : 1;
275 UINT64 Avx512Support : 1;
276 UINT64 Avx512DQSupport : 1;
277 UINT64 Avx512CDSupport : 1;
278 UINT64 Avx512BWSupport : 1;
279 UINT64 Avx512VLSupport : 1;
280 UINT64 XsaveCompSupport : 1;
281 UINT64 XsaveSupervisorSupport : 1;
282 UINT64 Xcr1Support : 1;
283 UINT64 Avx512BitalgSupport : 1;
284 UINT64 Avx512IfmaSupport : 1;
285 UINT64 Avx512VBmiSupport : 1;
286 UINT64 Avx512VBmi2Support : 1;
287 UINT64 Avx512VnniSupport : 1;
288 UINT64 GfniSupport : 1;
289 UINT64 VaesSupport : 1;
290 UINT64 Avx512VPopcntdqSupport : 1;
291 UINT64 VpclmulqdqSupport : 1;
292 UINT64 Avx512Bf16Support : 1;
293 UINT64 Avx512Vp2IntersectSupport : 1;
294 UINT64 Avx512Fp16Support : 1;
295 UINT64 XfdSupport : 1;
296 UINT64 AmxTileSupport : 1;
297 UINT64 AmxBf16Support : 1;
298 UINT64 AmxInt8Support : 1;
299 UINT64 AvxVnniSupport : 1;
300 UINT64 Reserved : 33;
301 };
302 UINT64 AsUINT64;
303} WHV_PROCESSOR_XSAVE_FEATURES, *PWHV_PROCESSOR_XSAVE_FEATURES;
304
305C_ASSERT(sizeof(WHV_PROCESSOR_XSAVE_FEATURES) == sizeof(UINT64));
306
307typedef union WHV_PROCESSOR_PERFMON_FEATURES {
308 __C89_NAMELESS struct {
309 UINT64 PmuSupport : 1;
310 UINT64 LbrSupport : 1;
311 UINT64 Reserved : 62;
312 };
313 UINT64 AsUINT64;
314} WHV_PROCESSOR_PERFMON_FEATURES, *PWHV_PROCESSOR_PERFMON_FEATURES;
315
316C_ASSERT(sizeof(WHV_PROCESSOR_PERFMON_FEATURES) == 8);
317
318typedef union WHV_X64_MSR_EXIT_BITMAP {
319 UINT64 AsUINT64;
320 __C89_NAMELESS struct {
321 UINT64 UnhandledMsrs : 1;
322 UINT64 TscMsrWrite : 1;
323 UINT64 TscMsrRead : 1;
324 UINT64 ApicBaseMsrWrite : 1;
325 UINT64 MiscEnableMsrRead:1;
326 UINT64 McUpdatePatchLevelMsrRead:1;
327 UINT64 Reserved:58;
328 };
329} WHV_X64_MSR_EXIT_BITMAP;
330
331C_ASSERT(sizeof(WHV_X64_MSR_EXIT_BITMAP) == sizeof(UINT64));
332
333typedef struct WHV_MEMORY_RANGE_ENTRY {
334 UINT64 GuestAddress;
335 UINT64 SizeInBytes;
336} WHV_MEMORY_RANGE_ENTRY;
337
338C_ASSERT(sizeof(WHV_MEMORY_RANGE_ENTRY) == 16);
339
340typedef union WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS {
341 UINT32 AsUINT32;
342 __C89_NAMELESS struct {
343 UINT32 Prefetch:1;
344 UINT32 AvoidHardFaults:1;
345 UINT32 Reserved:30;
346 };
347} WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS;
348
349C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS) == 4);
350
351typedef enum WHV_MEMORY_ACCESS_TYPE {
352 WHvMemoryAccessRead = 0,
353 WHvMemoryAccessWrite = 1,
354 WHvMemoryAccessExecute = 2
355} WHV_MEMORY_ACCESS_TYPE;
356
357typedef struct WHV_ADVISE_GPA_RANGE_POPULATE {
358 WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS Flags;
359 WHV_MEMORY_ACCESS_TYPE AccessType;
360} WHV_ADVISE_GPA_RANGE_POPULATE;
361
362C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE_POPULATE) == 8);
363
364typedef struct WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP {
365 UINT32 IsSupported:1;
366 UINT32 Reserved:31;
367 UINT32 HighestFrequencyMhz;
368 UINT32 NominalFrequencyMhz;
369 UINT32 LowestFrequencyMhz;
370 UINT32 FrequencyStepMhz;
371} WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP;
372
373C_ASSERT(sizeof(WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP) == 20);
374
375typedef union WHV_SCHEDULER_FEATURES {
376 __C89_NAMELESS struct {
377 UINT64 CpuReserve: 1;
378 UINT64 CpuCap: 1;
379 UINT64 CpuWeight: 1;
380 UINT64 CpuGroupId: 1;
381 UINT64 DisableSmt: 1;
382 UINT64 Reserved: 59;
383 };
384 UINT64 AsUINT64;
385} WHV_SCHEDULER_FEATURES;
386
387C_ASSERT(sizeof(WHV_SCHEDULER_FEATURES) == 8);
388
389typedef union WHV_CAPABILITY {
390 WINBOOL HypervisorPresent;
391 WHV_CAPABILITY_FEATURES Features;
392 WHV_EXTENDED_VM_EXITS ExtendedVmExits;
393 WHV_PROCESSOR_VENDOR ProcessorVendor;
394 WHV_PROCESSOR_FEATURES ProcessorFeatures;
395 WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS SyntheticProcessorFeaturesBanks;
396 WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
397 UINT8 ProcessorClFlushSize;
398 UINT64 ExceptionExitBitmap;
399 WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
400 UINT64 ProcessorClockFrequency;
401 UINT64 InterruptClockFrequency;
402 WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
403 WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS GpaRangePopulateFlags;
404 WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP ProcessorFrequencyCap;
405 WHV_PROCESSOR_PERFMON_FEATURES ProcessorPerfmonFeatures;
406 WHV_SCHEDULER_FEATURES SchedulerFeatures;
407} WHV_CAPABILITY;
408
409typedef VOID* WHV_PARTITION_HANDLE;
410
411typedef enum WHV_PARTITION_PROPERTY_CODE {
412 WHvPartitionPropertyCodeExtendedVmExits = 0x00000001,
413 WHvPartitionPropertyCodeExceptionExitBitmap = 0x00000002,
414 WHvPartitionPropertyCodeSeparateSecurityDomain = 0x00000003,
415 WHvPartitionPropertyCodeNestedVirtualization = 0x00000004,
416 WHvPartitionPropertyCodeX64MsrExitBitmap = 0x00000005,
417 WHvPartitionPropertyCodePrimaryNumaNode = 0x00000006,
418 WHvPartitionPropertyCodeCpuReserve = 0x00000007,
419 WHvPartitionPropertyCodeCpuCap = 0x00000008,
420 WHvPartitionPropertyCodeCpuWeight = 0x00000009,
421 WHvPartitionPropertyCodeCpuGroupId = 0x0000000A,
422 WHvPartitionPropertyCodeProcessorFrequencyCap = 0x0000000B,
423 WHvPartitionPropertyCodeAllowDeviceAssignment = 0x0000000C,
424 WHvPartitionPropertyCodeDisableSmt = 0x0000000D,
425 WHvPartitionPropertyCodeProcessorFeatures = 0x00001001,
426 WHvPartitionPropertyCodeProcessorClFlushSize = 0x00001002,
427 WHvPartitionPropertyCodeCpuidExitList = 0x00001003,
428 WHvPartitionPropertyCodeCpuidResultList = 0x00001004,
429 WHvPartitionPropertyCodeLocalApicEmulationMode = 0x00001005,
430 WHvPartitionPropertyCodeProcessorXsaveFeatures = 0x00001006,
431 WHvPartitionPropertyCodeProcessorClockFrequency = 0x00001007,
432 WHvPartitionPropertyCodeInterruptClockFrequency = 0x00001008,
433 WHvPartitionPropertyCodeApicRemoteReadSupport = 0x00001009,
434 WHvPartitionPropertyCodeProcessorFeaturesBanks = 0x0000100A,
435 WHvPartitionPropertyCodeReferenceTime = 0x0000100B,
436 WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks = 0x0000100C,
437 WHvPartitionPropertyCodeCpuidResultList2 = 0x0000100D,
438 WHvPartitionPropertyCodeProcessorPerfmonFeatures = 0x0000100E,
439 WHvPartitionPropertyCodeMsrActionList = 0x0000100F,
440 WHvPartitionPropertyCodeUnimplementedMsrAction = 0x00001010,
441 WHvPartitionPropertyCodeProcessorCount = 0x00001fff
442} WHV_PARTITION_PROPERTY_CODE;
443
444typedef struct WHV_X64_CPUID_RESULT {
445 UINT32 Function;
446 UINT32 Reserved[3];
447 UINT32 Eax;
448 UINT32 Ebx;
449 UINT32 Ecx;
450 UINT32 Edx;
451} WHV_X64_CPUID_RESULT;
452
453C_ASSERT(sizeof(WHV_X64_CPUID_RESULT) == 32);
454
455typedef enum WHV_X64_CPUID_RESULT2_FLAGS {
456 WHvX64CpuidResult2FlagSubleafSpecific = 0x00000001,
457 WHvX64CpuidResult2FlagVpSpecific = 0x00000002
458} WHV_X64_CPUID_RESULT2_FLAGS;
459
460DEFINE_ENUM_FLAG_OPERATORS(WHV_X64_CPUID_RESULT2_FLAGS);
461
462typedef struct WHV_CPUID_OUTPUT {
463 UINT32 Eax;
464 UINT32 Ebx;
465 UINT32 Ecx;
466 UINT32 Edx;
467} WHV_CPUID_OUTPUT;
468
469C_ASSERT(sizeof(WHV_CPUID_OUTPUT) == 16);
470
471typedef struct WHV_X64_CPUID_RESULT2 {
472 UINT32 Function;
473 UINT32 Index;
474 UINT32 VpIndex;
475 WHV_X64_CPUID_RESULT2_FLAGS Flags;
476 WHV_CPUID_OUTPUT Output;
477 WHV_CPUID_OUTPUT Mask;
478} WHV_X64_CPUID_RESULT2;
479
480C_ASSERT(sizeof(WHV_X64_CPUID_RESULT2) == 48);
481
482typedef struct WHV_MSR_ACTION_ENTRY {
483 UINT32 Index;
484 UINT8 ReadAction;
485 UINT8 WriteAction;
486 UINT16 Reserved;
487} WHV_MSR_ACTION_ENTRY;
488
489C_ASSERT(sizeof(WHV_MSR_ACTION_ENTRY) == 8);
490
491typedef enum WHV_MSR_ACTION {
492 WHvMsrActionArchitectureDefault = 0,
493 WHvMsrActionIgnoreWriteReadZero = 1,
494 WHvMsrActionExit = 2
495} WHV_MSR_ACTION;
496
497typedef enum WHV_EXCEPTION_TYPE {
498 WHvX64ExceptionTypeDivideErrorFault = 0x0,
499 WHvX64ExceptionTypeDebugTrapOrFault = 0x1,
500 WHvX64ExceptionTypeBreakpointTrap = 0x3,
501 WHvX64ExceptionTypeOverflowTrap = 0x4,
502 WHvX64ExceptionTypeBoundRangeFault = 0x5,
503 WHvX64ExceptionTypeInvalidOpcodeFault = 0x6,
504 WHvX64ExceptionTypeDeviceNotAvailableFault = 0x7,
505 WHvX64ExceptionTypeDoubleFaultAbort = 0x8,
506 WHvX64ExceptionTypeInvalidTaskStateSegmentFault = 0x0A,
507 WHvX64ExceptionTypeSegmentNotPresentFault = 0x0B,
508 WHvX64ExceptionTypeStackFault = 0x0C,
509 WHvX64ExceptionTypeGeneralProtectionFault = 0x0D,
510 WHvX64ExceptionTypePageFault = 0x0E,
511 WHvX64ExceptionTypeFloatingPointErrorFault = 0x10,
512 WHvX64ExceptionTypeAlignmentCheckFault = 0x11,
513 WHvX64ExceptionTypeMachineCheckAbort = 0x12,
514 WHvX64ExceptionTypeSimdFloatingPointFault = 0x13
515} WHV_EXCEPTION_TYPE;
516
517typedef enum WHV_X64_LOCAL_APIC_EMULATION_MODE {
518 WHvX64LocalApicEmulationModeNone,
519 WHvX64LocalApicEmulationModeXApic,
520 WHvX64LocalApicEmulationModeX2Apic
521} WHV_X64_LOCAL_APIC_EMULATION_MODE;
522
523typedef union WHV_PARTITION_PROPERTY {
524 WHV_EXTENDED_VM_EXITS ExtendedVmExits;
525 WHV_PROCESSOR_FEATURES ProcessorFeatures;
526 WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS SyntheticProcessorFeaturesBanks;
527 WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
528 UINT8 ProcessorClFlushSize;
529 UINT32 ProcessorCount;
530 UINT32 CpuidExitList[1];
531 WHV_X64_CPUID_RESULT CpuidResultList[1];
532 WHV_X64_CPUID_RESULT2 CpuidResultList2[1];
533 WHV_MSR_ACTION_ENTRY MsrActionList[1];
534 WHV_MSR_ACTION UnimplementedMsrAction;
535 UINT64 ExceptionExitBitmap;
536 WHV_X64_LOCAL_APIC_EMULATION_MODE LocalApicEmulationMode;
537 WINBOOL SeparateSecurityDomain;
538 WINBOOL NestedVirtualization;
539 WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
540 UINT64 ProcessorClockFrequency;
541 UINT64 InterruptClockFrequency;
542 WINBOOL ApicRemoteRead;
543 WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
544 UINT64 ReferenceTime;
545 USHORT PrimaryNumaNode;
546 UINT32 CpuReserve;
547 UINT32 CpuCap;
548 UINT32 CpuWeight;
549 UINT64 CpuGroupId;
550 UINT32 ProcessorFrequencyCap;
551 WINBOOL AllowDeviceAssignment;
552 WHV_PROCESSOR_PERFMON_FEATURES ProcessorPerfmonFeatures;
553 WINBOOL DisableSmt;
554} WHV_PARTITION_PROPERTY;
555
556typedef UINT64 WHV_GUEST_PHYSICAL_ADDRESS;
557typedef UINT64 WHV_GUEST_VIRTUAL_ADDRESS;
558
559typedef enum WHV_MAP_GPA_RANGE_FLAGS {
560 WHvMapGpaRangeFlagNone = 0x00000000,
561 WHvMapGpaRangeFlagRead = 0x00000001,
562 WHvMapGpaRangeFlagWrite = 0x00000002,
563 WHvMapGpaRangeFlagExecute = 0x00000004,
564 WHvMapGpaRangeFlagTrackDirtyPages = 0x00000008
565} WHV_MAP_GPA_RANGE_FLAGS;
566
567DEFINE_ENUM_FLAG_OPERATORS(WHV_MAP_GPA_RANGE_FLAGS);
568
569typedef enum WHV_TRANSLATE_GVA_FLAGS {
570 WHvTranslateGvaFlagNone = 0x00000000,
571 WHvTranslateGvaFlagValidateRead = 0x00000001,
572 WHvTranslateGvaFlagValidateWrite = 0x00000002,
573 WHvTranslateGvaFlagValidateExecute = 0x00000004,
574 WHvTranslateGvaFlagPrivilegeExempt = 0x00000008,
575 WHvTranslateGvaFlagSetPageTableBits = 0x00000010,
576 WHvTranslateGvaFlagEnforceSmap = 0x00000100,
577 WHvTranslateGvaFlagOverrideSmap = 0x00000200
578} WHV_TRANSLATE_GVA_FLAGS;
579
580DEFINE_ENUM_FLAG_OPERATORS(WHV_TRANSLATE_GVA_FLAGS);
581
582typedef enum WHV_TRANSLATE_GVA_RESULT_CODE {
583 WHvTranslateGvaResultSuccess = 0,
584 WHvTranslateGvaResultPageNotPresent = 1,
585 WHvTranslateGvaResultPrivilegeViolation = 2,
586 WHvTranslateGvaResultInvalidPageTableFlags = 3,
587 WHvTranslateGvaResultGpaUnmapped = 4,
588 WHvTranslateGvaResultGpaNoReadAccess = 5,
589 WHvTranslateGvaResultGpaNoWriteAccess = 6,
590 WHvTranslateGvaResultGpaIllegalOverlayAccess = 7,
591 WHvTranslateGvaResultIntercept = 8
592} WHV_TRANSLATE_GVA_RESULT_CODE;
593
594typedef struct WHV_TRANSLATE_GVA_RESULT {
595 WHV_TRANSLATE_GVA_RESULT_CODE ResultCode;
596 UINT32 Reserved;
597} WHV_TRANSLATE_GVA_RESULT;
598
599C_ASSERT(sizeof(WHV_TRANSLATE_GVA_RESULT) == 8);
600
601typedef union WHV_ADVISE_GPA_RANGE {
602 WHV_ADVISE_GPA_RANGE_POPULATE Populate;
603} WHV_ADVISE_GPA_RANGE;
604
605C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE) == 8);
606
607typedef enum WHV_CACHE_TYPE {
608 WHvCacheTypeUncached = 0,
609 WHvCacheTypeWriteCombining = 1,
610 WHvCacheTypeWriteThrough = 4,
611#ifdef __x86_64__
612 WHvCacheTypeWriteProtected = 5,
613#endif
614 WHvCacheTypeWriteBack = 6
615} WHV_CACHE_TYPE;
616
617typedef union WHV_ACCESS_GPA_CONTROLS {
618 UINT64 AsUINT64;
619 __C89_NAMELESS struct {
620 WHV_CACHE_TYPE CacheType;
621 UINT32 Reserved;
622 };
623} WHV_ACCESS_GPA_CONTROLS;
624
625C_ASSERT(sizeof(WHV_ACCESS_GPA_CONTROLS) == 8);
626
627#define WHV_READ_WRITE_GPA_RANGE_MAX_SIZE 16
628
629typedef enum WHV_REGISTER_NAME {
630 WHvX64RegisterRax = 0x00000000,
631 WHvX64RegisterRcx = 0x00000001,
632 WHvX64RegisterRdx = 0x00000002,
633 WHvX64RegisterRbx = 0x00000003,
634 WHvX64RegisterRsp = 0x00000004,
635 WHvX64RegisterRbp = 0x00000005,
636 WHvX64RegisterRsi = 0x00000006,
637 WHvX64RegisterRdi = 0x00000007,
638 WHvX64RegisterR8 = 0x00000008,
639 WHvX64RegisterR9 = 0x00000009,
640 WHvX64RegisterR10 = 0x0000000A,
641 WHvX64RegisterR11 = 0x0000000B,
642 WHvX64RegisterR12 = 0x0000000C,
643 WHvX64RegisterR13 = 0x0000000D,
644 WHvX64RegisterR14 = 0x0000000E,
645 WHvX64RegisterR15 = 0x0000000F,
646 WHvX64RegisterRip = 0x00000010,
647 WHvX64RegisterRflags = 0x00000011,
648 WHvX64RegisterEs = 0x00000012,
649 WHvX64RegisterCs = 0x00000013,
650 WHvX64RegisterSs = 0x00000014,
651 WHvX64RegisterDs = 0x00000015,
652 WHvX64RegisterFs = 0x00000016,
653 WHvX64RegisterGs = 0x00000017,
654 WHvX64RegisterLdtr = 0x00000018,
655 WHvX64RegisterTr = 0x00000019,
656 WHvX64RegisterIdtr = 0x0000001A,
657 WHvX64RegisterGdtr = 0x0000001B,
658 WHvX64RegisterCr0 = 0x0000001C,
659 WHvX64RegisterCr2 = 0x0000001D,
660 WHvX64RegisterCr3 = 0x0000001E,
661 WHvX64RegisterCr4 = 0x0000001F,
662 WHvX64RegisterCr8 = 0x00000020,
663 WHvX64RegisterDr0 = 0x00000021,
664 WHvX64RegisterDr1 = 0x00000022,
665 WHvX64RegisterDr2 = 0x00000023,
666 WHvX64RegisterDr3 = 0x00000024,
667 WHvX64RegisterDr6 = 0x00000025,
668 WHvX64RegisterDr7 = 0x00000026,
669 WHvX64RegisterXCr0 = 0x00000027,
670 WHvX64RegisterVirtualCr0 = 0x00000028,
671 WHvX64RegisterVirtualCr3 = 0x00000029,
672 WHvX64RegisterVirtualCr4 = 0x0000002A,
673 WHvX64RegisterVirtualCr8 = 0x0000002B,
674 WHvX64RegisterXmm0 = 0x00001000,
675 WHvX64RegisterXmm1 = 0x00001001,
676 WHvX64RegisterXmm2 = 0x00001002,
677 WHvX64RegisterXmm3 = 0x00001003,
678 WHvX64RegisterXmm4 = 0x00001004,
679 WHvX64RegisterXmm5 = 0x00001005,
680 WHvX64RegisterXmm6 = 0x00001006,
681 WHvX64RegisterXmm7 = 0x00001007,
682 WHvX64RegisterXmm8 = 0x00001008,
683 WHvX64RegisterXmm9 = 0x00001009,
684 WHvX64RegisterXmm10 = 0x0000100A,
685 WHvX64RegisterXmm11 = 0x0000100B,
686 WHvX64RegisterXmm12 = 0x0000100C,
687 WHvX64RegisterXmm13 = 0x0000100D,
688 WHvX64RegisterXmm14 = 0x0000100E,
689 WHvX64RegisterXmm15 = 0x0000100F,
690 WHvX64RegisterFpMmx0 = 0x00001010,
691 WHvX64RegisterFpMmx1 = 0x00001011,
692 WHvX64RegisterFpMmx2 = 0x00001012,
693 WHvX64RegisterFpMmx3 = 0x00001013,
694 WHvX64RegisterFpMmx4 = 0x00001014,
695 WHvX64RegisterFpMmx5 = 0x00001015,
696 WHvX64RegisterFpMmx6 = 0x00001016,
697 WHvX64RegisterFpMmx7 = 0x00001017,
698 WHvX64RegisterFpControlStatus = 0x00001018,
699 WHvX64RegisterXmmControlStatus = 0x00001019,
700 WHvX64RegisterTsc = 0x00002000,
701 WHvX64RegisterEfer = 0x00002001,
702 WHvX64RegisterKernelGsBase = 0x00002002,
703 WHvX64RegisterApicBase = 0x00002003,
704 WHvX64RegisterPat = 0x00002004,
705 WHvX64RegisterSysenterCs = 0x00002005,
706 WHvX64RegisterSysenterEip = 0x00002006,
707 WHvX64RegisterSysenterEsp = 0x00002007,
708 WHvX64RegisterStar = 0x00002008,
709 WHvX64RegisterLstar = 0x00002009,
710 WHvX64RegisterCstar = 0x0000200A,
711 WHvX64RegisterSfmask = 0x0000200B,
712 WHvX64RegisterInitialApicId = 0x0000200C,
713 WHvX64RegisterMsrMtrrCap = 0x0000200D,
714 WHvX64RegisterMsrMtrrDefType = 0x0000200E,
715 WHvX64RegisterMsrMtrrPhysBase0 = 0x00002010,
716 WHvX64RegisterMsrMtrrPhysBase1 = 0x00002011,
717 WHvX64RegisterMsrMtrrPhysBase2 = 0x00002012,
718 WHvX64RegisterMsrMtrrPhysBase3 = 0x00002013,
719 WHvX64RegisterMsrMtrrPhysBase4 = 0x00002014,
720 WHvX64RegisterMsrMtrrPhysBase5 = 0x00002015,
721 WHvX64RegisterMsrMtrrPhysBase6 = 0x00002016,
722 WHvX64RegisterMsrMtrrPhysBase7 = 0x00002017,
723 WHvX64RegisterMsrMtrrPhysBase8 = 0x00002018,
724 WHvX64RegisterMsrMtrrPhysBase9 = 0x00002019,
725 WHvX64RegisterMsrMtrrPhysBaseA = 0x0000201A,
726 WHvX64RegisterMsrMtrrPhysBaseB = 0x0000201B,
727 WHvX64RegisterMsrMtrrPhysBaseC = 0x0000201C,
728 WHvX64RegisterMsrMtrrPhysBaseD = 0x0000201D,
729 WHvX64RegisterMsrMtrrPhysBaseE = 0x0000201E,
730 WHvX64RegisterMsrMtrrPhysBaseF = 0x0000201F,
731 WHvX64RegisterMsrMtrrPhysMask0 = 0x00002040,
732 WHvX64RegisterMsrMtrrPhysMask1 = 0x00002041,
733 WHvX64RegisterMsrMtrrPhysMask2 = 0x00002042,
734 WHvX64RegisterMsrMtrrPhysMask3 = 0x00002043,
735 WHvX64RegisterMsrMtrrPhysMask4 = 0x00002044,
736 WHvX64RegisterMsrMtrrPhysMask5 = 0x00002045,
737 WHvX64RegisterMsrMtrrPhysMask6 = 0x00002046,
738 WHvX64RegisterMsrMtrrPhysMask7 = 0x00002047,
739 WHvX64RegisterMsrMtrrPhysMask8 = 0x00002048,
740 WHvX64RegisterMsrMtrrPhysMask9 = 0x00002049,
741 WHvX64RegisterMsrMtrrPhysMaskA = 0x0000204A,
742 WHvX64RegisterMsrMtrrPhysMaskB = 0x0000204B,
743 WHvX64RegisterMsrMtrrPhysMaskC = 0x0000204C,
744 WHvX64RegisterMsrMtrrPhysMaskD = 0x0000204D,
745 WHvX64RegisterMsrMtrrPhysMaskE = 0x0000204E,
746 WHvX64RegisterMsrMtrrPhysMaskF = 0x0000204F,
747 WHvX64RegisterMsrMtrrFix64k00000 = 0x00002070,
748 WHvX64RegisterMsrMtrrFix16k80000 = 0x00002071,
749 WHvX64RegisterMsrMtrrFix16kA0000 = 0x00002072,
750 WHvX64RegisterMsrMtrrFix4kC0000 = 0x00002073,
751 WHvX64RegisterMsrMtrrFix4kC8000 = 0x00002074,
752 WHvX64RegisterMsrMtrrFix4kD0000 = 0x00002075,
753 WHvX64RegisterMsrMtrrFix4kD8000 = 0x00002076,
754 WHvX64RegisterMsrMtrrFix4kE0000 = 0x00002077,
755 WHvX64RegisterMsrMtrrFix4kE8000 = 0x00002078,
756 WHvX64RegisterMsrMtrrFix4kF0000 = 0x00002079,
757 WHvX64RegisterMsrMtrrFix4kF8000 = 0x0000207A,
758 WHvX64RegisterTscAux = 0x0000207B,
759 WHvX64RegisterBndcfgs = 0x0000207C,
760 WHvX64RegisterMCount = 0x0000207E,
761 WHvX64RegisterACount = 0x0000207F,
762 WHvX64RegisterSpecCtrl = 0x00002084,
763 WHvX64RegisterPredCmd = 0x00002085,
764 WHvX64RegisterTscVirtualOffset = 0x00002087,
765 WHvX64RegisterTsxCtrl = 0x00002088,
766 WHvX64RegisterXss = 0x0000208B,
767 WHvX64RegisterUCet = 0x0000208C,
768 WHvX64RegisterSCet = 0x0000208D,
769 WHvX64RegisterSsp = 0x0000208E,
770 WHvX64RegisterPl0Ssp = 0x0000208F,
771 WHvX64RegisterPl1Ssp = 0x00002090,
772 WHvX64RegisterPl2Ssp = 0x00002091,
773 WHvX64RegisterPl3Ssp = 0x00002092,
774 WHvX64RegisterInterruptSspTableAddr = 0x00002093,
775 WHvX64RegisterTscDeadline = 0x00002095,
776 WHvX64RegisterTscAdjust = 0x00002096,
777 WHvX64RegisterUmwaitControl = 0x00002098,
778 WHvX64RegisterXfd = 0x00002099,
779 WHvX64RegisterXfdErr = 0x0000209A,
780 WHvX64RegisterApicId = 0x00003002,
781 WHvX64RegisterApicVersion = 0x00003003,
782 WHvX64RegisterApicTpr = 0x00003008,
783 WHvX64RegisterApicPpr = 0x0000300A,
784 WHvX64RegisterApicEoi = 0x0000300B,
785 WHvX64RegisterApicLdr = 0x0000300D,
786 WHvX64RegisterApicSpurious = 0x0000300F,
787 WHvX64RegisterApicIsr0 = 0x00003010,
788 WHvX64RegisterApicIsr1 = 0x00003011,
789 WHvX64RegisterApicIsr2 = 0x00003012,
790 WHvX64RegisterApicIsr3 = 0x00003013,
791 WHvX64RegisterApicIsr4 = 0x00003014,
792 WHvX64RegisterApicIsr5 = 0x00003015,
793 WHvX64RegisterApicIsr6 = 0x00003016,
794 WHvX64RegisterApicIsr7 = 0x00003017,
795 WHvX64RegisterApicTmr0 = 0x00003018,
796 WHvX64RegisterApicTmr1 = 0x00003019,
797 WHvX64RegisterApicTmr2 = 0x0000301A,
798 WHvX64RegisterApicTmr3 = 0x0000301B,
799 WHvX64RegisterApicTmr4 = 0x0000301C,
800 WHvX64RegisterApicTmr5 = 0x0000301D,
801 WHvX64RegisterApicTmr6 = 0x0000301E,
802 WHvX64RegisterApicTmr7 = 0x0000301F,
803 WHvX64RegisterApicIrr0 = 0x00003020,
804 WHvX64RegisterApicIrr1 = 0x00003021,
805 WHvX64RegisterApicIrr2 = 0x00003022,
806 WHvX64RegisterApicIrr3 = 0x00003023,
807 WHvX64RegisterApicIrr4 = 0x00003024,
808 WHvX64RegisterApicIrr5 = 0x00003025,
809 WHvX64RegisterApicIrr6 = 0x00003026,
810 WHvX64RegisterApicIrr7 = 0x00003027,
811 WHvX64RegisterApicEse = 0x00003028,
812 WHvX64RegisterApicIcr = 0x00003030,
813 WHvX64RegisterApicLvtTimer = 0x00003032,
814 WHvX64RegisterApicLvtThermal = 0x00003033,
815 WHvX64RegisterApicLvtPerfmon = 0x00003034,
816 WHvX64RegisterApicLvtLint0 = 0x00003035,
817 WHvX64RegisterApicLvtLint1 = 0x00003036,
818 WHvX64RegisterApicLvtError = 0x00003037,
819 WHvX64RegisterApicInitCount = 0x00003038,
820 WHvX64RegisterApicCurrentCount = 0x00003039,
821 WHvX64RegisterApicDivide = 0x0000303E,
822 WHvX64RegisterApicSelfIpi = 0x0000303F,
823 WHvRegisterSint0 = 0x00004000,
824 WHvRegisterSint1 = 0x00004001,
825 WHvRegisterSint2 = 0x00004002,
826 WHvRegisterSint3 = 0x00004003,
827 WHvRegisterSint4 = 0x00004004,
828 WHvRegisterSint5 = 0x00004005,
829 WHvRegisterSint6 = 0x00004006,
830 WHvRegisterSint7 = 0x00004007,
831 WHvRegisterSint8 = 0x00004008,
832 WHvRegisterSint9 = 0x00004009,
833 WHvRegisterSint10 = 0x0000400A,
834 WHvRegisterSint11 = 0x0000400B,
835 WHvRegisterSint12 = 0x0000400C,
836 WHvRegisterSint13 = 0x0000400D,
837 WHvRegisterSint14 = 0x0000400E,
838 WHvRegisterSint15 = 0x0000400F,
839 WHvRegisterScontrol = 0x00004010,
840 WHvRegisterSversion = 0x00004011,
841 WHvRegisterSiefp = 0x00004012,
842 WHvRegisterSimp = 0x00004013,
843 WHvRegisterEom = 0x00004014,
844 WHvRegisterVpRuntime = 0x00005000,
845 WHvX64RegisterHypercall = 0x00005001,
846 WHvRegisterGuestOsId = 0x00005002,
847 WHvRegisterVpAssistPage = 0x00005013,
848 WHvRegisterReferenceTsc = 0x00005017,
849 WHvRegisterReferenceTscSequence = 0x0000501A,
850 WHvRegisterPendingInterruption = 0x80000000,
851 WHvRegisterInterruptState = 0x80000001,
852 WHvRegisterPendingEvent = 0x80000002,
853 WHvX64RegisterDeliverabilityNotifications = 0x80000004,
854 WHvRegisterInternalActivityState = 0x80000005,
855 WHvX64RegisterPendingDebugException = 0x80000006
856} WHV_REGISTER_NAME;
857
858typedef union DECLSPEC_ALIGN(16) WHV_UINT128 {
859 __C89_NAMELESS struct {
860 UINT64 Low64;
861 UINT64 High64;
862 };
863 UINT32 Dword[4];
864} WHV_UINT128;
865
866C_ASSERT(sizeof(WHV_UINT128) == 16);
867
868typedef union WHV_X64_FP_REGISTER {
869 __C89_NAMELESS struct {
870 UINT64 Mantissa;
871 UINT64 BiasedExponent:15;
872 UINT64 Sign:1;
873 UINT64 Reserved:48;
874 };
875 WHV_UINT128 AsUINT128;
876} WHV_X64_FP_REGISTER;
877
878C_ASSERT(sizeof(WHV_X64_FP_REGISTER) == 16);
879
880typedef union WHV_X64_FP_CONTROL_STATUS_REGISTER {
881 __C89_NAMELESS struct {
882 UINT16 FpControl;
883 UINT16 FpStatus;
884 UINT8 FpTag;
885 UINT8 Reserved;
886 UINT16 LastFpOp;
887 __C89_NAMELESS union {
888 UINT64 LastFpRip;
889 __C89_NAMELESS struct {
890 UINT32 LastFpEip;
891 UINT16 LastFpCs;
892 UINT16 Reserved2;
893 };
894 };
895 };
896 WHV_UINT128 AsUINT128;
897} WHV_X64_FP_CONTROL_STATUS_REGISTER;
898
899C_ASSERT(sizeof(WHV_X64_FP_CONTROL_STATUS_REGISTER) == 16);
900
901typedef union WHV_X64_XMM_CONTROL_STATUS_REGISTER {
902 __C89_NAMELESS struct {
903 __C89_NAMELESS union {
904 UINT64 LastFpRdp;
905 __C89_NAMELESS struct {
906 UINT32 LastFpDp;
907 UINT16 LastFpDs;
908 UINT16 Reserved;
909 };
910 };
911 UINT32 XmmStatusControl;
912 UINT32 XmmStatusControlMask;
913 };
914 WHV_UINT128 AsUINT128;
915} WHV_X64_XMM_CONTROL_STATUS_REGISTER;
916
917C_ASSERT(sizeof(WHV_X64_FP_CONTROL_STATUS_REGISTER) == 16);
918
919typedef struct WHV_X64_SEGMENT_REGISTER {
920 UINT64 Base;
921 UINT32 Limit;
922 UINT16 Selector;
923 __C89_NAMELESS union {
924 __C89_NAMELESS struct {
925 UINT16 SegmentType:4;
926 UINT16 NonSystemSegment:1;
927 UINT16 DescriptorPrivilegeLevel:2;
928 UINT16 Present:1;
929 UINT16 Reserved:4;
930 UINT16 Available:1;
931 UINT16 Long:1;
932 UINT16 Default:1;
933 UINT16 Granularity:1;
934 };
935 UINT16 Attributes;
936 };
937} WHV_X64_SEGMENT_REGISTER;
938
939C_ASSERT(sizeof(WHV_X64_SEGMENT_REGISTER) == 16);
940
941typedef struct WHV_X64_TABLE_REGISTER {
942 UINT16 Pad[3];
943 UINT16 Limit;
944 UINT64 Base;
945} WHV_X64_TABLE_REGISTER;
946
947C_ASSERT(sizeof(WHV_X64_TABLE_REGISTER) == 16);
948
949typedef union WHV_X64_INTERRUPT_STATE_REGISTER {
950 __C89_NAMELESS struct {
951 UINT64 InterruptShadow:1;
952 UINT64 NmiMasked:1;
953 UINT64 Reserved:62;
954 };
955 UINT64 AsUINT64;
956} WHV_X64_INTERRUPT_STATE_REGISTER;
957
958C_ASSERT(sizeof(WHV_X64_INTERRUPT_STATE_REGISTER) == 8);
959
960typedef union WHV_X64_PENDING_INTERRUPTION_REGISTER {
961 __C89_NAMELESS struct {
962 UINT32 InterruptionPending:1;
963 UINT32 InterruptionType:3;
964 UINT32 DeliverErrorCode:1;
965 UINT32 InstructionLength:4;
966 UINT32 NestedEvent:1;
967 UINT32 Reserved:6;
968 UINT32 InterruptionVector:16;
969 UINT32 ErrorCode;
970 };
971 UINT64 AsUINT64;
972} WHV_X64_PENDING_INTERRUPTION_REGISTER;
973
974C_ASSERT(sizeof(WHV_X64_PENDING_INTERRUPTION_REGISTER) == sizeof(UINT64));
975
976typedef union WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER {
977 __C89_NAMELESS struct {
978 UINT64 NmiNotification:1;
979 UINT64 InterruptNotification:1;
980 UINT64 InterruptPriority:4;
981 UINT64 Reserved:58;
982 };
983 UINT64 AsUINT64;
984} WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER;
985
986C_ASSERT(sizeof(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) == sizeof(UINT64));
987
988typedef enum WHV_X64_PENDING_EVENT_TYPE {
989 WHvX64PendingEventException = 0,
990 WHvX64PendingEventExtInt = 5
991} WHV_X64_PENDING_EVENT_TYPE;
992
993typedef union WHV_X64_PENDING_EXCEPTION_EVENT {
994 __C89_NAMELESS struct {
995 UINT32 EventPending : 1;
996 UINT32 EventType : 3;
997 UINT32 Reserved0 : 4;
998 UINT32 DeliverErrorCode : 1;
999 UINT32 Reserved1 : 7;
1000 UINT32 Vector : 16;
1001 UINT32 ErrorCode;
1002 UINT64 ExceptionParameter;
1003 };
1004 WHV_UINT128 AsUINT128;
1005} WHV_X64_PENDING_EXCEPTION_EVENT;
1006
1007C_ASSERT(sizeof(WHV_X64_PENDING_EXCEPTION_EVENT) == sizeof(WHV_UINT128));
1008
1009typedef union WHV_X64_PENDING_EXT_INT_EVENT {
1010 __C89_NAMELESS struct {
1011 UINT64 EventPending : 1;
1012 UINT64 EventType : 3;
1013 UINT64 Reserved0 : 4;
1014 UINT64 Vector : 8;
1015 UINT64 Reserved1 : 48;
1016 UINT64 Reserved2;
1017 };
1018 WHV_UINT128 AsUINT128;
1019} WHV_X64_PENDING_EXT_INT_EVENT;
1020
1021C_ASSERT(sizeof(WHV_X64_PENDING_EXT_INT_EVENT) == sizeof(WHV_UINT128));
1022
1023typedef union WHV_INTERNAL_ACTIVITY_REGISTER {
1024 __C89_NAMELESS struct {
1025 UINT64 StartupSuspend : 1;
1026 UINT64 HaltSuspend : 1;
1027 UINT64 IdleSuspend : 1;
1028 UINT64 Reserved :61;
1029 };
1030 UINT64 AsUINT64;
1031} WHV_INTERNAL_ACTIVITY_REGISTER;
1032
1033C_ASSERT(sizeof(WHV_INTERNAL_ACTIVITY_REGISTER) == sizeof(UINT64));
1034
1035typedef union WHV_X64_PENDING_DEBUG_EXCEPTION {
1036 UINT64 AsUINT64;
1037 __C89_NAMELESS struct {
1038 UINT64 Breakpoint0 : 1;
1039 UINT64 Breakpoint1 : 1;
1040 UINT64 Breakpoint2 : 1;
1041 UINT64 Breakpoint3 : 1;
1042 UINT64 SingleStep : 1;
1043 UINT64 Reserved0 : 59;
1044 };
1045} WHV_X64_PENDING_DEBUG_EXCEPTION;
1046
1047C_ASSERT(sizeof(WHV_X64_PENDING_DEBUG_EXCEPTION) == sizeof(UINT64));
1048
1049typedef struct WHV_SYNIC_SINT_DELIVERABLE_CONTEXT {
1050 UINT16 DeliverableSints;
1051 UINT16 Reserved1;
1052 UINT32 Reserved2;
1053} WHV_SYNIC_SINT_DELIVERABLE_CONTEXT;
1054
1055C_ASSERT(sizeof(WHV_SYNIC_SINT_DELIVERABLE_CONTEXT) == 8);
1056
1057typedef union WHV_REGISTER_VALUE {
1058 WHV_UINT128 Reg128;
1059 UINT64 Reg64;
1060 UINT32 Reg32;
1061 UINT16 Reg16;
1062 UINT8 Reg8;
1063 WHV_X64_FP_REGISTER Fp;
1064 WHV_X64_FP_CONTROL_STATUS_REGISTER FpControlStatus;
1065 WHV_X64_XMM_CONTROL_STATUS_REGISTER XmmControlStatus;
1066 WHV_X64_SEGMENT_REGISTER Segment;
1067 WHV_X64_TABLE_REGISTER Table;
1068 WHV_X64_INTERRUPT_STATE_REGISTER InterruptState;
1069 WHV_X64_PENDING_INTERRUPTION_REGISTER PendingInterruption;
1070 WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER DeliverabilityNotifications;
1071 WHV_X64_PENDING_EXCEPTION_EVENT ExceptionEvent;
1072 WHV_X64_PENDING_EXT_INT_EVENT ExtIntEvent;
1073 WHV_INTERNAL_ACTIVITY_REGISTER InternalActivity;
1074 WHV_X64_PENDING_DEBUG_EXCEPTION PendingDebugException;
1075} WHV_REGISTER_VALUE;
1076
1077C_ASSERT(sizeof(WHV_REGISTER_VALUE) == 16);
1078
1079typedef enum WHV_RUN_VP_EXIT_REASON {
1080 WHvRunVpExitReasonNone = 0x00000000,
1081 WHvRunVpExitReasonMemoryAccess = 0x00000001,
1082 WHvRunVpExitReasonX64IoPortAccess = 0x00000002,
1083 WHvRunVpExitReasonUnrecoverableException = 0x00000004,
1084 WHvRunVpExitReasonInvalidVpRegisterValue = 0x00000005,
1085 WHvRunVpExitReasonUnsupportedFeature = 0x00000006,
1086 WHvRunVpExitReasonX64InterruptWindow = 0x00000007,
1087 WHvRunVpExitReasonX64Halt = 0x00000008,
1088 WHvRunVpExitReasonX64ApicEoi = 0x00000009,
1089 WHvRunVpExitReasonSynicSintDeliverable = 0x0000000A,
1090 WHvRunVpExitReasonX64MsrAccess = 0x00001000,
1091 WHvRunVpExitReasonX64Cpuid = 0x00001001,
1092 WHvRunVpExitReasonException = 0x00001002,
1093 WHvRunVpExitReasonX64Rdtsc = 0x00001003,
1094 WHvRunVpExitReasonX64ApicSmiTrap = 0x00001004,
1095 WHvRunVpExitReasonHypercall = 0x00001005,
1096 WHvRunVpExitReasonX64ApicInitSipiTrap = 0x00001006,
1097 WHvRunVpExitReasonX64ApicWriteTrap = 0x00001007,
1098 WHvRunVpExitReasonCanceled = 0x00002001
1099} WHV_RUN_VP_EXIT_REASON;
1100
1101typedef union WHV_X64_VP_EXECUTION_STATE {
1102 __C89_NAMELESS struct {
1103 UINT16 Cpl : 2;
1104 UINT16 Cr0Pe : 1;
1105 UINT16 Cr0Am : 1;
1106 UINT16 EferLma : 1;
1107 UINT16 DebugActive : 1;
1108 UINT16 InterruptionPending : 1;
1109 UINT16 Reserved0 : 5;
1110 UINT16 InterruptShadow : 1;
1111 UINT16 Reserved1 : 3;
1112 };
1113 UINT16 AsUINT16;
1114} WHV_X64_VP_EXECUTION_STATE;
1115
1116C_ASSERT(sizeof(WHV_X64_VP_EXECUTION_STATE) == sizeof(UINT16));
1117
1118typedef struct WHV_VP_EXIT_CONTEXT {
1119 WHV_X64_VP_EXECUTION_STATE ExecutionState;
1120 UINT8 InstructionLength : 4;
1121 UINT8 Cr8 : 4;
1122 UINT8 Reserved;
1123 UINT32 Reserved2;
1124 WHV_X64_SEGMENT_REGISTER Cs;
1125 UINT64 Rip;
1126 UINT64 Rflags;
1127} WHV_VP_EXIT_CONTEXT;
1128
1129C_ASSERT(sizeof(WHV_VP_EXIT_CONTEXT) == 40);
1130
1131typedef union WHV_MEMORY_ACCESS_INFO {
1132 __C89_NAMELESS struct {
1133 UINT32 AccessType : 2;
1134 UINT32 GpaUnmapped : 1;
1135 UINT32 GvaValid : 1;
1136 UINT32 Reserved : 28;
1137 };
1138 UINT32 AsUINT32;
1139} WHV_MEMORY_ACCESS_INFO;
1140
1141C_ASSERT(sizeof(WHV_MEMORY_ACCESS_INFO) == 4);
1142
1143typedef struct WHV_MEMORY_ACCESS_CONTEXT {
1144 UINT8 InstructionByteCount;
1145 UINT8 Reserved[3];
1146 UINT8 InstructionBytes[16];
1147 WHV_MEMORY_ACCESS_INFO AccessInfo;
1148 WHV_GUEST_PHYSICAL_ADDRESS Gpa;
1149 WHV_GUEST_VIRTUAL_ADDRESS Gva;
1150} WHV_MEMORY_ACCESS_CONTEXT;
1151
1152C_ASSERT(sizeof(WHV_MEMORY_ACCESS_CONTEXT) == 40);
1153
1154typedef union WHV_X64_IO_PORT_ACCESS_INFO {
1155 __C89_NAMELESS struct {
1156 UINT32 IsWrite : 1;
1157 UINT32 AccessSize: 3;
1158 UINT32 StringOp : 1;
1159 UINT32 RepPrefix : 1;
1160 UINT32 Reserved : 26;
1161 };
1162 UINT32 AsUINT32;
1163} WHV_X64_IO_PORT_ACCESS_INFO;
1164
1165C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_INFO) == sizeof(UINT32));
1166
1167typedef struct WHV_X64_IO_PORT_ACCESS_CONTEXT {
1168 UINT8 InstructionByteCount;
1169 UINT8 Reserved[3];
1170 UINT8 InstructionBytes[16];
1171 WHV_X64_IO_PORT_ACCESS_INFO AccessInfo;
1172 UINT16 PortNumber;
1173 UINT16 Reserved2[3];
1174 UINT64 Rax;
1175 UINT64 Rcx;
1176 UINT64 Rsi;
1177 UINT64 Rdi;
1178 WHV_X64_SEGMENT_REGISTER Ds;
1179 WHV_X64_SEGMENT_REGISTER Es;
1180} WHV_X64_IO_PORT_ACCESS_CONTEXT;
1181
1182C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_CONTEXT) == 96);
1183
1184typedef union WHV_X64_MSR_ACCESS_INFO {
1185 __C89_NAMELESS struct {
1186 UINT32 IsWrite : 1;
1187 UINT32 Reserved : 31;
1188 };
1189 UINT32 AsUINT32;
1190} WHV_X64_MSR_ACCESS_INFO;
1191
1192C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_INFO) == sizeof(UINT32));
1193
1194typedef struct WHV_X64_MSR_ACCESS_CONTEXT {
1195 WHV_X64_MSR_ACCESS_INFO AccessInfo;
1196 UINT32 MsrNumber;
1197 UINT64 Rax;
1198 UINT64 Rdx;
1199} WHV_X64_MSR_ACCESS_CONTEXT;
1200
1201C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_CONTEXT) == 24);
1202
1203typedef struct WHV_X64_CPUID_ACCESS_CONTEXT {
1204 UINT64 Rax;
1205 UINT64 Rcx;
1206 UINT64 Rdx;
1207 UINT64 Rbx;
1208 UINT64 DefaultResultRax;
1209 UINT64 DefaultResultRcx;
1210 UINT64 DefaultResultRdx;
1211 UINT64 DefaultResultRbx;
1212} WHV_X64_CPUID_ACCESS_CONTEXT;
1213
1214C_ASSERT(sizeof(WHV_X64_CPUID_ACCESS_CONTEXT) == 64);
1215
1216typedef union WHV_VP_EXCEPTION_INFO {
1217 __C89_NAMELESS struct {
1218 UINT32 ErrorCodeValid : 1;
1219 UINT32 SoftwareException : 1;
1220 UINT32 Reserved : 30;
1221 };
1222 UINT32 AsUINT32;
1223} WHV_VP_EXCEPTION_INFO;
1224
1225C_ASSERT(sizeof(WHV_VP_EXCEPTION_INFO) == sizeof(UINT32));
1226
1227typedef struct WHV_VP_EXCEPTION_CONTEXT {
1228 UINT8 InstructionByteCount;
1229 UINT8 Reserved[3];
1230 UINT8 InstructionBytes[16];
1231 WHV_VP_EXCEPTION_INFO ExceptionInfo;
1232 UINT8 ExceptionType;
1233 UINT8 Reserved2[3];
1234 UINT32 ErrorCode;
1235 UINT64 ExceptionParameter;
1236} WHV_VP_EXCEPTION_CONTEXT;
1237
1238C_ASSERT(sizeof(WHV_VP_EXCEPTION_CONTEXT) == 40);
1239
1240typedef enum WHV_X64_UNSUPPORTED_FEATURE_CODE {
1241 WHvUnsupportedFeatureIntercept = 1,
1242 WHvUnsupportedFeatureTaskSwitchTss = 2
1243} WHV_X64_UNSUPPORTED_FEATURE_CODE;
1244
1245typedef struct WHV_X64_UNSUPPORTED_FEATURE_CONTEXT {
1246 WHV_X64_UNSUPPORTED_FEATURE_CODE FeatureCode;
1247 UINT32 Reserved;
1248 UINT64 FeatureParameter;
1249} WHV_X64_UNSUPPORTED_FEATURE_CONTEXT;
1250
1251C_ASSERT(sizeof(WHV_X64_UNSUPPORTED_FEATURE_CONTEXT) == 16);
1252
1253typedef enum WHV_RUN_VP_CANCEL_REASON {
1254 WhvRunVpCancelReasonUser = 0
1255} WHV_RUN_VP_CANCEL_REASON;
1256
1257typedef struct WHV_RUN_VP_CANCELED_CONTEXT {
1258 WHV_RUN_VP_CANCEL_REASON CancelReason;
1259} WHV_RUN_VP_CANCELED_CONTEXT;
1260
1261C_ASSERT(sizeof(WHV_RUN_VP_CANCELED_CONTEXT) == 4);
1262
1263typedef enum WHV_X64_PENDING_INTERRUPTION_TYPE {
1264 WHvX64PendingInterrupt = 0,
1265 WHvX64PendingNmi = 2,
1266 WHvX64PendingException = 3
1267} WHV_X64_PENDING_INTERRUPTION_TYPE, *PWHV_X64_PENDING_INTERRUPTION_TYPE;
1268
1269typedef struct WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT {
1270 WHV_X64_PENDING_INTERRUPTION_TYPE DeliverableType;
1271} WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT, *PWHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT;
1272
1273C_ASSERT(sizeof(WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT) == 4);
1274
1275typedef struct WHV_X64_APIC_EOI_CONTEXT {
1276 UINT32 InterruptVector;
1277} WHV_X64_APIC_EOI_CONTEXT;
1278
1279C_ASSERT(sizeof(WHV_X64_APIC_EOI_CONTEXT) == 4);
1280
1281typedef union WHV_X64_RDTSC_INFO {
1282 __C89_NAMELESS struct {
1283 UINT64 IsRdtscp : 1;
1284 UINT64 Reserved : 63;
1285 };
1286 UINT64 AsUINT64;
1287} WHV_X64_RDTSC_INFO;
1288
1289C_ASSERT(sizeof(WHV_X64_RDTSC_INFO) == 8);
1290
1291typedef struct WHV_X64_RDTSC_CONTEXT {
1292 UINT64 TscAux;
1293 UINT64 VirtualOffset;
1294 UINT64 Tsc;
1295 UINT64 ReferenceTime;
1296 WHV_X64_RDTSC_INFO RdtscInfo;
1297} WHV_X64_RDTSC_CONTEXT;
1298
1299C_ASSERT(sizeof(WHV_X64_RDTSC_CONTEXT) == 40);
1300
1301typedef struct WHV_X64_APIC_SMI_CONTEXT {
1302 UINT64 ApicIcr;
1303} WHV_X64_APIC_SMI_CONTEXT;
1304
1305C_ASSERT(sizeof(WHV_X64_APIC_SMI_CONTEXT) == 8);
1306
1307#define WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS 6
1308
1309typedef struct _WHV_HYPERCALL_CONTEXT {
1310 UINT64 Rax;
1311 UINT64 Rbx;
1312 UINT64 Rcx;
1313 UINT64 Rdx;
1314 UINT64 R8;
1315 UINT64 Rsi;
1316 UINT64 Rdi;
1317 UINT64 Reserved0;
1318 WHV_UINT128 XmmRegisters[WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS];
1319 UINT64 Reserved1[2];
1320} WHV_HYPERCALL_CONTEXT, *PWHV_HYPERCALL_CONTEXT;
1321
1322C_ASSERT(sizeof(WHV_HYPERCALL_CONTEXT) == 176);
1323
1324typedef struct WHV_X64_APIC_INIT_SIPI_CONTEXT {
1325 UINT64 ApicIcr;
1326} WHV_X64_APIC_INIT_SIPI_CONTEXT;
1327
1328C_ASSERT(sizeof(WHV_X64_APIC_INIT_SIPI_CONTEXT) == 8);
1329
1330typedef enum WHV_X64_APIC_WRITE_TYPE {
1331 WHvX64ApicWriteTypeLdr = 0xD0,
1332 WHvX64ApicWriteTypeDfr = 0xE0,
1333 WHvX64ApicWriteTypeSvr = 0xF0,
1334 WHvX64ApicWriteTypeLint0 = 0x350,
1335 WHvX64ApicWriteTypeLint1 = 0x360
1336} WHV_X64_APIC_WRITE_TYPE;
1337
1338typedef struct WHV_X64_APIC_WRITE_CONTEXT {
1339 WHV_X64_APIC_WRITE_TYPE Type;
1340 UINT32 Reserved;
1341 UINT64 WriteValue;
1342} WHV_X64_APIC_WRITE_CONTEXT;
1343
1344C_ASSERT(sizeof(WHV_X64_APIC_WRITE_CONTEXT) == 16);
1345
1346typedef struct WHV_RUN_VP_EXIT_CONTEXT {
1347 WHV_RUN_VP_EXIT_REASON ExitReason;
1348 UINT32 Reserved;
1349 WHV_VP_EXIT_CONTEXT VpContext;
1350 __C89_NAMELESS union {
1351 WHV_MEMORY_ACCESS_CONTEXT MemoryAccess;
1352 WHV_X64_IO_PORT_ACCESS_CONTEXT IoPortAccess;
1353 WHV_X64_MSR_ACCESS_CONTEXT MsrAccess;
1354 WHV_X64_CPUID_ACCESS_CONTEXT CpuidAccess;
1355 WHV_VP_EXCEPTION_CONTEXT VpException;
1356 WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT InterruptWindow;
1357 WHV_X64_UNSUPPORTED_FEATURE_CONTEXT UnsupportedFeature;
1358 WHV_RUN_VP_CANCELED_CONTEXT CancelReason;
1359 WHV_X64_APIC_EOI_CONTEXT ApicEoi;
1360 WHV_X64_RDTSC_CONTEXT ReadTsc;
1361 WHV_X64_APIC_SMI_CONTEXT ApicSmi;
1362 WHV_HYPERCALL_CONTEXT Hypercall;
1363 WHV_X64_APIC_INIT_SIPI_CONTEXT ApicInitSipi;
1364 WHV_X64_APIC_WRITE_CONTEXT ApicWrite;
1365 WHV_SYNIC_SINT_DELIVERABLE_CONTEXT SynicSintDeliverable;
1366 };
1367} WHV_RUN_VP_EXIT_CONTEXT;
1368
1369C_ASSERT(sizeof(WHV_RUN_VP_EXIT_CONTEXT) == 224);
1370
1371typedef enum WHV_INTERRUPT_TYPE {
1372 WHvX64InterruptTypeFixed = 0,
1373 WHvX64InterruptTypeLowestPriority = 1,
1374 WHvX64InterruptTypeNmi = 4,
1375 WHvX64InterruptTypeInit = 5,
1376 WHvX64InterruptTypeSipi = 6,
1377 WHvX64InterruptTypeLocalInt1 = 9
1378} WHV_INTERRUPT_TYPE;
1379
1380typedef enum WHV_INTERRUPT_DESTINATION_MODE {
1381 WHvX64InterruptDestinationModePhysical,
1382 WHvX64InterruptDestinationModeLogical
1383} WHV_INTERRUPT_DESTINATION_MODE;
1384
1385typedef enum WHV_INTERRUPT_TRIGGER_MODE {
1386 WHvX64InterruptTriggerModeEdge,
1387 WHvX64InterruptTriggerModeLevel
1388} WHV_INTERRUPT_TRIGGER_MODE;
1389
1390typedef struct WHV_INTERRUPT_CONTROL {
1391 UINT64 Type : 8;
1392 UINT64 DestinationMode : 4;
1393 UINT64 TriggerMode : 4;
1394 UINT64 Reserved : 48;
1395 UINT32 Destination;
1396 UINT32 Vector;
1397} WHV_INTERRUPT_CONTROL;
1398
1399C_ASSERT(sizeof(WHV_INTERRUPT_CONTROL) == 16);
1400
1401typedef struct WHV_DOORBELL_MATCH_DATA {
1402 WHV_GUEST_PHYSICAL_ADDRESS GuestAddress;
1403 UINT64 Value;
1404 UINT32 Length;
1405 UINT32 MatchOnValue : 1;
1406 UINT32 MatchOnLength : 1;
1407 UINT32 Reserved : 30;
1408} WHV_DOORBELL_MATCH_DATA;
1409
1410C_ASSERT(sizeof(WHV_DOORBELL_MATCH_DATA) == 24);
1411
1412typedef enum WHV_PARTITION_COUNTER_SET {
1413 WHvPartitionCounterSetMemory
1414} WHV_PARTITION_COUNTER_SET;
1415
1416typedef struct WHV_PARTITION_MEMORY_COUNTERS {
1417 UINT64 Mapped4KPageCount;
1418 UINT64 Mapped2MPageCount;
1419 UINT64 Mapped1GPageCount;
1420} WHV_PARTITION_MEMORY_COUNTERS;
1421
1422C_ASSERT(sizeof(WHV_PARTITION_MEMORY_COUNTERS) == 24);
1423
1424typedef enum WHV_PROCESSOR_COUNTER_SET {
1425 WHvProcessorCounterSetRuntime,
1426 WHvProcessorCounterSetIntercepts,
1427 WHvProcessorCounterSetEvents,
1428 WHvProcessorCounterSetApic,
1429 WHvProcessorCounterSetSyntheticFeatures
1430} WHV_PROCESSOR_COUNTER_SET;
1431
1432typedef struct WHV_PROCESSOR_RUNTIME_COUNTERS {
1433 UINT64 TotalRuntime100ns;
1434 UINT64 HypervisorRuntime100ns;
1435} WHV_PROCESSOR_RUNTIME_COUNTERS;
1436
1437C_ASSERT(sizeof(WHV_PROCESSOR_RUNTIME_COUNTERS) == 16);
1438
1439typedef struct WHV_PROCESSOR_INTERCEPT_COUNTER {
1440 UINT64 Count;
1441 UINT64 Time100ns;
1442} WHV_PROCESSOR_INTERCEPT_COUNTER;
1443
1444C_ASSERT(sizeof(WHV_PROCESSOR_INTERCEPT_COUNTER) == 16);
1445
1446typedef struct WHV_PROCESSOR_INTERCEPT_COUNTERS {
1447 WHV_PROCESSOR_INTERCEPT_COUNTER PageInvalidations;
1448 WHV_PROCESSOR_INTERCEPT_COUNTER ControlRegisterAccesses;
1449 WHV_PROCESSOR_INTERCEPT_COUNTER IoInstructions;
1450 WHV_PROCESSOR_INTERCEPT_COUNTER HaltInstructions;
1451 WHV_PROCESSOR_INTERCEPT_COUNTER CpuidInstructions;
1452 WHV_PROCESSOR_INTERCEPT_COUNTER MsrAccesses;
1453 WHV_PROCESSOR_INTERCEPT_COUNTER OtherIntercepts;
1454 WHV_PROCESSOR_INTERCEPT_COUNTER PendingInterrupts;
1455 WHV_PROCESSOR_INTERCEPT_COUNTER EmulatedInstructions;
1456 WHV_PROCESSOR_INTERCEPT_COUNTER DebugRegisterAccesses;
1457 WHV_PROCESSOR_INTERCEPT_COUNTER PageFaultIntercepts;
1458 WHV_PROCESSOR_INTERCEPT_COUNTER NestedPageFaultIntercepts;
1459 WHV_PROCESSOR_INTERCEPT_COUNTER Hypercalls;
1460 WHV_PROCESSOR_INTERCEPT_COUNTER RdpmcInstructions;
1461} WHV_PROCESSOR_ACTIVITY_COUNTERS;
1462
1463C_ASSERT(sizeof(WHV_PROCESSOR_ACTIVITY_COUNTERS) == 224);
1464
1465typedef struct WHV_PROCESSOR_EVENT_COUNTERS {
1466 UINT64 PageFaultCount;
1467 UINT64 ExceptionCount;
1468 UINT64 InterruptCount;
1469} WHV_PROCESSOR_GUEST_EVENT_COUNTERS;
1470
1471C_ASSERT(sizeof(WHV_PROCESSOR_GUEST_EVENT_COUNTERS) == 24);
1472
1473typedef struct WHV_PROCESSOR_APIC_COUNTERS {
1474 UINT64 MmioAccessCount;
1475 UINT64 EoiAccessCount;
1476 UINT64 TprAccessCount;
1477 UINT64 SentIpiCount;
1478 UINT64 SelfIpiCount;
1479} WHV_PROCESSOR_APIC_COUNTERS;
1480
1481C_ASSERT(sizeof(WHV_PROCESSOR_APIC_COUNTERS) == 40);
1482
1483typedef struct WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS {
1484 UINT64 SyntheticInterruptsCount;
1485 UINT64 LongSpinWaitHypercallsCount;
1486 UINT64 OtherHypercallsCount;
1487 UINT64 SyntheticInterruptHypercallsCount;
1488 UINT64 VirtualInterruptHypercallsCount;
1489 UINT64 VirtualMmuHypercallsCount;
1490} WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS;
1491
1492C_ASSERT(sizeof(WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS) == 48);
1493
1494typedef enum WHV_ADVISE_GPA_RANGE_CODE {
1495 WHvAdviseGpaRangeCodePopulate = 0x00000000,
1496 WHvAdviseGpaRangeCodePin = 0x00000001,
1497 WHvAdviseGpaRangeCodeUnpin = 0x00000002
1498} WHV_ADVISE_GPA_RANGE_CODE;
1499
1500typedef enum WHV_VIRTUAL_PROCESSOR_STATE_TYPE {
1501 WHvVirtualProcessorStateTypeSynicMessagePage = 0x00000000,
1502 WHvVirtualProcessorStateTypeSynicEventFlagPage = 0x00000001,
1503 WHvVirtualProcessorStateTypeSynicTimerState = 0x00000002,
1504 WHvVirtualProcessorStateTypeInterruptControllerState2 = 0x00001000,
1505 WHvVirtualProcessorStateTypeXsaveState = 0x00001001
1506} WHV_VIRTUAL_PROCESSOR_STATE_TYPE;
1507
1508typedef struct WHV_SYNIC_EVENT_PARAMETERS {
1509 UINT32 VpIndex;
1510 UINT8 TargetSint;
1511 UINT8 Reserved;
1512 UINT16 FlagNumber;
1513} WHV_SYNIC_EVENT_PARAMETERS;
1514
1515C_ASSERT(sizeof(WHV_SYNIC_EVENT_PARAMETERS) == 8);
1516
1517typedef enum WHV_ALLOCATE_VPCI_RESOURCE_FLAGS {
1518 WHvAllocateVpciResourceFlagNone = 0x00000000,
1519 WHvAllocateVpciResourceFlagAllowDirectP2P = 0x00000001
1520} WHV_ALLOCATE_VPCI_RESOURCE_FLAGS;
1521
1522DEFINE_ENUM_FLAG_OPERATORS(WHV_ALLOCATE_VPCI_RESOURCE_FLAGS);
1523
1524#define WHV_MAX_DEVICE_ID_SIZE_IN_CHARS 200
1525
1526typedef struct WHV_SRIOV_RESOURCE_DESCRIPTOR {
1527 WCHAR PnpInstanceId[WHV_MAX_DEVICE_ID_SIZE_IN_CHARS];
1528 LUID VirtualFunctionId;
1529 UINT16 VirtualFunctionIndex;
1530 UINT16 Reserved;
1531} WHV_SRIOV_RESOURCE_DESCRIPTOR;
1532
1533C_ASSERT(sizeof(WHV_SRIOV_RESOURCE_DESCRIPTOR) == 412);
1534
1535typedef enum WHV_VPCI_DEVICE_NOTIFICATION_TYPE {
1536 WHvVpciDeviceNotificationUndefined = 0,
1537 WHvVpciDeviceNotificationMmioRemapping = 1,
1538 WHvVpciDeviceNotificationSurpriseRemoval = 2
1539} WHV_VPCI_DEVICE_NOTIFICATION_TYPE;
1540
1541typedef struct WHV_VPCI_DEVICE_NOTIFICATION {
1542 WHV_VPCI_DEVICE_NOTIFICATION_TYPE NotificationType;
1543 UINT32 Reserved1;
1544 __C89_NAMELESS union {
1545 UINT64 Reserved2;
1546 };
1547} WHV_VPCI_DEVICE_NOTIFICATION;
1548
1549C_ASSERT(sizeof(WHV_VPCI_DEVICE_NOTIFICATION) == 16);
1550
1551typedef enum WHV_CREATE_VPCI_DEVICE_FLAGS {
1552 WHvCreateVpciDeviceFlagNone = 0x00000000,
1553 WHvCreateVpciDeviceFlagPhysicallyBacked = 0x00000001,
1554 WHvCreateVpciDeviceFlagUseLogicalInterrupts = 0x00000002
1555} WHV_CREATE_VPCI_DEVICE_FLAGS;
1556
1557DEFINE_ENUM_FLAG_OPERATORS(WHV_CREATE_VPCI_DEVICE_FLAGS);
1558
1559typedef enum WHV_VPCI_DEVICE_PROPERTY_CODE {
1560 WHvVpciDevicePropertyCodeUndefined = 0,
1561 WHvVpciDevicePropertyCodeHardwareIDs = 1,
1562 WHvVpciDevicePropertyCodeProbedBARs = 2
1563} WHV_VPCI_DEVICE_PROPERTY_CODE;
1564
1565typedef struct WHV_VPCI_HARDWARE_IDS {
1566 UINT16 VendorID;
1567 UINT16 DeviceID;
1568 UINT8 RevisionID;
1569 UINT8 ProgIf;
1570 UINT8 SubClass;
1571 UINT8 BaseClass;
1572 UINT16 SubVendorID;
1573 UINT16 SubSystemID;
1574} WHV_VPCI_HARDWARE_IDS;
1575
1576C_ASSERT(sizeof(WHV_VPCI_HARDWARE_IDS) == 12);
1577
1578#define WHV_VPCI_TYPE0_BAR_COUNT 6
1579
1580typedef struct WHV_VPCI_PROBED_BARS {
1581 UINT32 Value[WHV_VPCI_TYPE0_BAR_COUNT];
1582} WHV_VPCI_PROBED_BARS;
1583
1584C_ASSERT(sizeof(WHV_VPCI_PROBED_BARS) == 24);
1585
1586typedef enum WHV_VPCI_MMIO_RANGE_FLAGS {
1587 WHvVpciMmioRangeFlagReadAccess = 0x00000001,
1588 WHvVpciMmioRangeFlagWriteAccess = 0x00000002
1589} WHV_VPCI_MMIO_RANGE_FLAGS;
1590
1591DEFINE_ENUM_FLAG_OPERATORS(WHV_VPCI_MMIO_RANGE_FLAGS);
1592
1593typedef enum WHV_VPCI_DEVICE_REGISTER_SPACE {
1594 WHvVpciConfigSpace = -1,
1595 WHvVpciBar0 = 0,
1596 WHvVpciBar1 = 1,
1597 WHvVpciBar2 = 2,
1598 WHvVpciBar3 = 3,
1599 WHvVpciBar4 = 4,
1600 WHvVpciBar5 = 5
1601} WHV_VPCI_DEVICE_REGISTER_SPACE;
1602
1603typedef struct WHV_VPCI_MMIO_MAPPING {
1604 WHV_VPCI_DEVICE_REGISTER_SPACE Location;
1605 WHV_VPCI_MMIO_RANGE_FLAGS Flags;
1606 UINT64 SizeInBytes;
1607 UINT64 OffsetInBytes;
1608 PVOID VirtualAddress;
1609} WHV_VPCI_MMIO_MAPPING;
1610
1611C_ASSERT(sizeof(WHV_VPCI_MMIO_MAPPING) == 32);
1612
1613typedef struct WHV_VPCI_DEVICE_REGISTER {
1614 WHV_VPCI_DEVICE_REGISTER_SPACE Location;
1615 UINT32 SizeInBytes;
1616 UINT64 OffsetInBytes;
1617} WHV_VPCI_DEVICE_REGISTER;
1618
1619C_ASSERT(sizeof(WHV_VPCI_DEVICE_REGISTER) == 16);
1620
1621typedef enum WHV_VPCI_INTERRUPT_TARGET_FLAGS {
1622 WHvVpciInterruptTargetFlagNone = 0x00000000,
1623 WHvVpciInterruptTargetFlagMulticast = 0x00000001
1624} WHV_VPCI_INTERRUPT_TARGET_FLAGS;
1625
1626DEFINE_ENUM_FLAG_OPERATORS(WHV_VPCI_INTERRUPT_TARGET_FLAGS);
1627
1628typedef struct WHV_VPCI_INTERRUPT_TARGET {
1629 UINT32 Vector;
1630 WHV_VPCI_INTERRUPT_TARGET_FLAGS Flags;
1631 UINT32 ProcessorCount;
1632 UINT32 Processors[ANYSIZE_ARRAY];
1633} WHV_VPCI_INTERRUPT_TARGET;
1634
1635C_ASSERT(sizeof(WHV_VPCI_INTERRUPT_TARGET) == 16);
1636
1637typedef enum WHV_TRIGGER_TYPE {
1638 WHvTriggerTypeInterrupt = 0,
1639 WHvTriggerTypeSynicEvent = 1,
1640 WHvTriggerTypeDeviceInterrupt = 2
1641} WHV_TRIGGER_TYPE;
1642
1643typedef struct WHV_TRIGGER_PARAMETERS {
1644 WHV_TRIGGER_TYPE TriggerType;
1645 UINT32 Reserved;
1646 __C89_NAMELESS union {
1647 WHV_INTERRUPT_CONTROL Interrupt;
1648 WHV_SYNIC_EVENT_PARAMETERS SynicEvent;
1649 __C89_NAMELESS struct {
1650 UINT64 LogicalDeviceId;
1651 UINT64 MsiAddress;
1652 UINT32 MsiData;
1653 UINT32 Reserved;
1654 } DeviceInterrupt;
1655 };
1656} WHV_TRIGGER_PARAMETERS;
1657
1658C_ASSERT(sizeof(WHV_TRIGGER_PARAMETERS) == 32);
1659
1660typedef PVOID WHV_TRIGGER_HANDLE;
1661
1662typedef enum WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE {
1663 WHvVirtualProcessorPropertyCodeNumaNode = 0x00000000
1664} WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE;
1665
1666typedef struct WHV_VIRTUAL_PROCESSOR_PROPERTY {
1667 WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE PropertyCode;
1668 UINT32 Reserved;
1669 __C89_NAMELESS union {
1670 USHORT NumaNode;
1671 UINT64 Padding;
1672 };
1673} WHV_VIRTUAL_PROCESSOR_PROPERTY;
1674
1675C_ASSERT(sizeof(WHV_VIRTUAL_PROCESSOR_PROPERTY) == 16);
1676
1677typedef enum WHV_NOTIFICATION_PORT_TYPE {
1678 WHvNotificationPortTypeEvent = 2,
1679 WHvNotificationPortTypeDoorbell = 4
1680} WHV_NOTIFICATION_PORT_TYPE;
1681
1682typedef struct WHV_NOTIFICATION_PORT_PARAMETERS {
1683 WHV_NOTIFICATION_PORT_TYPE NotificationPortType;
1684 UINT32 Reserved;
1685 __C89_NAMELESS union {
1686 WHV_DOORBELL_MATCH_DATA Doorbell;
1687 __C89_NAMELESS struct {
1688 UINT32 ConnectionId;
1689 } Event;
1690 };
1691} WHV_NOTIFICATION_PORT_PARAMETERS;
1692
1693C_ASSERT(sizeof(WHV_NOTIFICATION_PORT_PARAMETERS) == 32);
1694
1695typedef enum WHV_NOTIFICATION_PORT_PROPERTY_CODE {
1696 WHvNotificationPortPropertyPreferredTargetVp = 1,
1697 WHvNotificationPortPropertyPreferredTargetDuration = 5
1698} WHV_NOTIFICATION_PORT_PROPERTY_CODE;
1699
1700typedef UINT64 WHV_NOTIFICATION_PORT_PROPERTY;
1701
1702#define WHV_ANY_VP (0xFFFFFFFF)
1703
1704#define WHV_NOTIFICATION_PORT_PREFERRED_DURATION_MAX (0xFFFFFFFFFFFFFFFFULL)
1705
1706typedef PVOID WHV_NOTIFICATION_PORT_HANDLE;
1707
1708#define WHV_SYNIC_MESSAGE_SIZE 256
1709
1710#endif /* _WINHVAPIDEFS_H_ */
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