| 1 | /*
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| 2 | * Copyright (C) 2007-2021 Free Software Foundation, Inc.
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| 3 | *
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| 4 | * This file is free software; you can redistribute it and/or modify it
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| 5 | * under the terms of the GNU General Public License as published by the
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| 6 | * Free Software Foundation; either version 3, or (at your option) any
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| 7 | * later version.
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| 8 | *
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| 9 | * This file is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * Under Section 7 of GPL version 3, you are granted additional
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| 15 | * permissions described in the GCC Runtime Library Exception, version
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| 16 | * 3.1, as published by the Free Software Foundation.
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| 17 | *
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| 18 | * You should have received a copy of the GNU General Public License and
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| 19 | * a copy of the GCC Runtime Library Exception along with this program;
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| 20 | * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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| 21 | * <http://www.gnu.org/licenses/>.
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| 22 | */
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| 23 |
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| 24 | #ifndef _CPUID_H_INCLUDED
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| 25 | #define _CPUID_H_INCLUDED
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| 26 |
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| 27 | /* %eax */
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| 28 | #define bit_AVXVNNI (1 << 4)
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| 29 | #define bit_AVX512BF16 (1 << 5)
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| 30 | #define bit_HRESET (1 << 22)
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| 31 |
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| 32 | /* %ecx */
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| 33 | #define bit_SSE3 (1 << 0)
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| 34 | #define bit_PCLMUL (1 << 1)
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| 35 | #define bit_LZCNT (1 << 5)
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| 36 | #define bit_SSSE3 (1 << 9)
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| 37 | #define bit_FMA (1 << 12)
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| 38 | #define bit_CMPXCHG16B (1 << 13)
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| 39 | #define bit_SSE4_1 (1 << 19)
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| 40 | #define bit_SSE4_2 (1 << 20)
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| 41 | #define bit_MOVBE (1 << 22)
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| 42 | #define bit_POPCNT (1 << 23)
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| 43 | #define bit_AES (1 << 25)
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| 44 | #define bit_XSAVE (1 << 26)
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| 45 | #define bit_OSXSAVE (1 << 27)
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| 46 | #define bit_AVX (1 << 28)
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| 47 | #define bit_F16C (1 << 29)
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| 48 | #define bit_RDRND (1 << 30)
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| 49 |
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| 50 | /* %edx */
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| 51 | #define bit_CMPXCHG8B (1 << 8)
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| 52 | #define bit_CMOV (1 << 15)
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| 53 | #define bit_MMX (1 << 23)
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| 54 | #define bit_FXSAVE (1 << 24)
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| 55 | #define bit_SSE (1 << 25)
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| 56 | #define bit_SSE2 (1 << 26)
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| 57 |
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| 58 | /* Extended Features (%eax == 0x80000001) */
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| 59 | /* %ecx */
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| 60 | #define bit_LAHF_LM (1 << 0)
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| 61 | #define bit_ABM (1 << 5)
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| 62 | #define bit_SSE4a (1 << 6)
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| 63 | #define bit_PRFCHW (1 << 8)
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| 64 | #define bit_XOP (1 << 11)
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| 65 | #define bit_LWP (1 << 15)
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| 66 | #define bit_FMA4 (1 << 16)
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| 67 | #define bit_TBM (1 << 21)
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| 68 | #define bit_MWAITX (1 << 29)
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| 69 |
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| 70 | /* %edx */
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| 71 | #define bit_MMXEXT (1 << 22)
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| 72 | #define bit_LM (1 << 29)
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| 73 | #define bit_3DNOWP (1 << 30)
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| 74 | #define bit_3DNOW (1u << 31)
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| 75 |
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| 76 | /* %ebx */
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| 77 | #define bit_CLZERO (1 << 0)
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| 78 | #define bit_WBNOINVD (1 << 9)
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| 79 |
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| 80 | /* Extended Features (%eax == 7) */
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| 81 | /* %ebx */
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| 82 | #define bit_FSGSBASE (1 << 0)
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| 83 | #define bit_SGX (1 << 2)
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| 84 | #define bit_BMI (1 << 3)
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| 85 | #define bit_HLE (1 << 4)
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| 86 | #define bit_AVX2 (1 << 5)
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| 87 | #define bit_BMI2 (1 << 8)
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| 88 | #define bit_RTM (1 << 11)
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| 89 | #define bit_MPX (1 << 14)
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| 90 | #define bit_AVX512F (1 << 16)
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| 91 | #define bit_AVX512DQ (1 << 17)
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| 92 | #define bit_RDSEED (1 << 18)
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| 93 | #define bit_ADX (1 << 19)
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| 94 | #define bit_AVX512IFMA (1 << 21)
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| 95 | #define bit_CLFLUSHOPT (1 << 23)
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| 96 | #define bit_CLWB (1 << 24)
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| 97 | #define bit_AVX512PF (1 << 26)
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| 98 | #define bit_AVX512ER (1 << 27)
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| 99 | #define bit_AVX512CD (1 << 28)
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| 100 | #define bit_SHA (1 << 29)
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| 101 | #define bit_AVX512BW (1 << 30)
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| 102 | #define bit_AVX512VL (1u << 31)
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| 103 |
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| 104 | /* %ecx */
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| 105 | #define bit_PREFETCHWT1 (1 << 0)
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| 106 | #define bit_AVX512VBMI (1 << 1)
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| 107 | #define bit_PKU (1 << 3)
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| 108 | #define bit_OSPKE (1 << 4)
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| 109 | #define bit_WAITPKG (1 << 5)
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| 110 | #define bit_AVX512VBMI2 (1 << 6)
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| 111 | #define bit_SHSTK (1 << 7)
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| 112 | #define bit_GFNI (1 << 8)
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| 113 | #define bit_VAES (1 << 9)
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| 114 | #define bit_AVX512VNNI (1 << 11)
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| 115 | #define bit_VPCLMULQDQ (1 << 10)
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| 116 | #define bit_AVX512BITALG (1 << 12)
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| 117 | #define bit_AVX512VPOPCNTDQ (1 << 14)
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| 118 | #define bit_RDPID (1 << 22)
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| 119 | #define bit_MOVDIRI (1 << 27)
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| 120 | #define bit_MOVDIR64B (1 << 28)
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| 121 | #define bit_ENQCMD (1 << 29)
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| 122 | #define bit_CLDEMOTE (1 << 25)
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| 123 | #define bit_KL (1 << 23)
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| 124 |
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| 125 | /* %edx */
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| 126 | #define bit_AVX5124VNNIW (1 << 2)
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| 127 | #define bit_AVX5124FMAPS (1 << 3)
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| 128 | #define bit_AVX512VP2INTERSECT (1 << 8)
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| 129 | #define bit_IBT (1 << 20)
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| 130 | #define bit_UINTR (1 << 5)
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| 131 | #define bit_PCONFIG (1 << 18)
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| 132 | #define bit_SERIALIZE (1 << 14)
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| 133 | #define bit_TSXLDTRK (1 << 16)
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| 134 | #define bit_AMX_BF16 (1 << 22)
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| 135 | #define bit_AMX_TILE (1 << 24)
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| 136 | #define bit_AMX_INT8 (1 << 25)
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| 137 |
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| 138 | /* XFEATURE_ENABLED_MASK register bits (%eax == 0xd, %ecx == 0) */
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| 139 | #define bit_BNDREGS (1 << 3)
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| 140 | #define bit_BNDCSR (1 << 4)
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| 141 |
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| 142 | /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
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| 143 | #define bit_XSAVEOPT (1 << 0)
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| 144 | #define bit_XSAVEC (1 << 1)
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| 145 | #define bit_XSAVES (1 << 3)
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| 146 |
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| 147 | /* PT sub leaf (%eax == 0x14, %ecx == 0) */
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| 148 | /* %ebx */
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| 149 | #define bit_PTWRITE (1 << 4)
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| 150 |
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| 151 | /* Keylocker leaf (%eax == 0x19) */
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| 152 | /* %ebx */
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| 153 | #define bit_AESKLE ( 1<<0 )
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| 154 | #define bit_WIDEKL ( 1<<2 )
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| 155 |
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| 156 |
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| 157 | /* Signatures for different CPU implementations as returned in uses
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| 158 | of cpuid with level 0. */
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| 159 | #define signature_AMD_ebx 0x68747541
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| 160 | #define signature_AMD_ecx 0x444d4163
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| 161 | #define signature_AMD_edx 0x69746e65
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| 162 |
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| 163 | #define signature_CENTAUR_ebx 0x746e6543
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| 164 | #define signature_CENTAUR_ecx 0x736c7561
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| 165 | #define signature_CENTAUR_edx 0x48727561
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| 166 |
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| 167 | #define signature_CYRIX_ebx 0x69727943
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| 168 | #define signature_CYRIX_ecx 0x64616574
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| 169 | #define signature_CYRIX_edx 0x736e4978
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| 170 |
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| 171 | #define signature_INTEL_ebx 0x756e6547
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| 172 | #define signature_INTEL_ecx 0x6c65746e
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| 173 | #define signature_INTEL_edx 0x49656e69
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| 174 |
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| 175 | #define signature_TM1_ebx 0x6e617254
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| 176 | #define signature_TM1_ecx 0x55504361
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| 177 | #define signature_TM1_edx 0x74656d73
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| 178 |
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| 179 | #define signature_TM2_ebx 0x756e6547
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| 180 | #define signature_TM2_ecx 0x3638784d
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| 181 | #define signature_TM2_edx 0x54656e69
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| 182 |
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| 183 | #define signature_NSC_ebx 0x646f6547
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| 184 | #define signature_NSC_ecx 0x43534e20
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| 185 | #define signature_NSC_edx 0x79622065
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| 186 |
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| 187 | #define signature_NEXGEN_ebx 0x4778654e
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| 188 | #define signature_NEXGEN_ecx 0x6e657669
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| 189 | #define signature_NEXGEN_edx 0x72446e65
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| 190 |
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| 191 | #define signature_RISE_ebx 0x65736952
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| 192 | #define signature_RISE_ecx 0x65736952
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| 193 | #define signature_RISE_edx 0x65736952
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| 194 |
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| 195 | #define signature_SIS_ebx 0x20536953
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| 196 | #define signature_SIS_ecx 0x20536953
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| 197 | #define signature_SIS_edx 0x20536953
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| 198 |
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| 199 | #define signature_UMC_ebx 0x20434d55
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| 200 | #define signature_UMC_ecx 0x20434d55
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| 201 | #define signature_UMC_edx 0x20434d55
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| 202 |
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| 203 | #define signature_VIA_ebx 0x20414956
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| 204 | #define signature_VIA_ecx 0x20414956
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| 205 | #define signature_VIA_edx 0x20414956
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| 206 |
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| 207 | #define signature_VORTEX_ebx 0x74726f56
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| 208 | #define signature_VORTEX_ecx 0x436f5320
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| 209 | #define signature_VORTEX_edx 0x36387865
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| 210 |
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| 211 | #ifndef __x86_64__
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| 212 | /* At least one cpu (Winchip 2) does not set %ebx and %ecx
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| 213 | for cpuid leaf 1. Forcibly zero the two registers before
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| 214 | calling cpuid as a precaution. */
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| 215 | #define __cpuid(level, a, b, c, d) \
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| 216 | do { \
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| 217 | if (__builtin_constant_p (level) && (level) != 1) \
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| 218 | __asm__ __volatile__ ("cpuid\n\t" \
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| 219 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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| 220 | : "0" (level)); \
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| 221 | else \
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| 222 | __asm__ __volatile__ ("cpuid\n\t" \
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| 223 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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| 224 | : "0" (level), "1" (0), "2" (0)); \
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| 225 | } while (0)
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| 226 | #else
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| 227 | #define __cpuid(level, a, b, c, d) \
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| 228 | __asm__ __volatile__ ("cpuid\n\t" \
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| 229 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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| 230 | : "0" (level))
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| 231 | #endif
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| 232 |
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| 233 | #define __cpuid_count(level, count, a, b, c, d) \
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| 234 | __asm__ __volatile__ ("cpuid\n\t" \
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| 235 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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| 236 | : "0" (level), "2" (count))
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| 237 |
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| 238 |
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| 239 | /* Return highest supported input value for cpuid instruction. ext can
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| 240 | be either 0x0 or 0x80000000 to return highest supported value for
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| 241 | basic or extended cpuid information. Function returns 0 if cpuid
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| 242 | is not supported or whatever cpuid returns in eax register. If sig
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| 243 | pointer is non-null, then first four bytes of the signature
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| 244 | (as found in ebx register) are returned in location pointed by sig. */
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| 245 |
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| 246 | static __inline unsigned int
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| 247 | __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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| 248 | {
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| 249 | unsigned int __eax, __ebx, __ecx, __edx;
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| 250 |
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| 251 | #ifndef __x86_64__
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| 252 | /* See if we can use cpuid. On AMD64 we always can. */
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| 253 | #if __GNUC__ >= 3
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| 254 | __asm__ ("pushf{l|d}\n\t"
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| 255 | "pushf{l|d}\n\t"
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| 256 | "pop{l}\t%0\n\t"
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| 257 | "mov{l}\t{%0, %1|%1, %0}\n\t"
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| 258 | "xor{l}\t{%2, %0|%0, %2}\n\t"
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| 259 | "push{l}\t%0\n\t"
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| 260 | "popf{l|d}\n\t"
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| 261 | "pushf{l|d}\n\t"
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| 262 | "pop{l}\t%0\n\t"
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| 263 | "popf{l|d}\n\t"
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| 264 | : "=&r" (__eax), "=&r" (__ebx)
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| 265 | : "i" (0x00200000));
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| 266 | #else
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| 267 | /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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| 268 | nor alternatives in i386 code. */
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| 269 | __asm__ ("pushfl\n\t"
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| 270 | "pushfl\n\t"
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| 271 | "popl\t%0\n\t"
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| 272 | "movl\t%0, %1\n\t"
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| 273 | "xorl\t%2, %0\n\t"
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| 274 | "pushl\t%0\n\t"
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| 275 | "popfl\n\t"
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| 276 | "pushfl\n\t"
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| 277 | "popl\t%0\n\t"
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| 278 | "popfl\n\t"
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| 279 | : "=&r" (__eax), "=&r" (__ebx)
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| 280 | : "i" (0x00200000));
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| 281 | #endif
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| 282 |
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| 283 | if (!((__eax ^ __ebx) & 0x00200000))
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| 284 | return 0;
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| 285 | #endif
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| 286 |
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| 287 | /* Host supports cpuid. Return highest supported cpuid input value. */
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| 288 | __cpuid (__ext, __eax, __ebx, __ecx, __edx);
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| 289 |
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| 290 | if (__sig)
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| 291 | *__sig = __ebx;
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| 292 |
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| 293 | return __eax;
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| 294 | }
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| 295 |
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| 296 | /* Return cpuid data for requested cpuid leaf, as found in returned
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| 297 | eax, ebx, ecx and edx registers. The function checks if cpuid is
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| 298 | supported and returns 1 for valid cpuid information or 0 for
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| 299 | unsupported cpuid leaf. All pointers are required to be non-null. */
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| 300 |
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| 301 | static __inline int
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| 302 | __get_cpuid (unsigned int __leaf,
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| 303 | unsigned int *__eax, unsigned int *__ebx,
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| 304 | unsigned int *__ecx, unsigned int *__edx)
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| 305 | {
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| 306 | unsigned int __ext = __leaf & 0x80000000;
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| 307 | unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
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| 308 |
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| 309 | if (__maxlevel == 0 || __maxlevel < __leaf)
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| 310 | return 0;
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| 311 |
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| 312 | __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
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| 313 | return 1;
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| 314 | }
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| 315 |
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| 316 | /* Same as above, but sub-leaf can be specified. */
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| 317 |
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| 318 | static __inline int
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| 319 | __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
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| 320 | unsigned int *__eax, unsigned int *__ebx,
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| 321 | unsigned int *__ecx, unsigned int *__edx)
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| 322 | {
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| 323 | unsigned int __ext = __leaf & 0x80000000;
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| 324 | unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
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| 325 |
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| 326 | if (__maxlevel == 0 || __maxlevel < __leaf)
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| 327 | return 0;
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| 328 |
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| 329 | __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
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| 330 | return 1;
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| 331 | }
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| 332 |
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| 333 | static __inline void
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| 334 | __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf)
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| 335 | {
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| 336 | __cpuid_count (__leaf, __subleaf, __cpuid_info[0], __cpuid_info[1],
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| 337 | __cpuid_info[2], __cpuid_info[3]);
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| 338 | }
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| 339 |
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| 340 | #endif /* _CPUID_H_INCLUDED */
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