source: Daodan/MinGW/include/ddk/parallel.h@ 1054

Last change on this file since 1054 was 1046, checked in by alloc, 8 years ago

Daodan: Added Windows MinGW and build batch file
File size: 8.6 KB
Line 
1/*
2 * parallel.h
3 *
4 * ParPort driver interface
5 *
6 * This file is part of the w32api package.
7 *
8 * Contributors:
9 * Created by Casper S. Hornstrup <chorns@users.sourceforge.net>
10 *
11 * THIS SOFTWARE IS NOT COPYRIGHTED
12 *
13 * This source code is offered for use in the public domain. You may
14 * use, modify or distribute it freely.
15 *
16 * This code is distributed in the hope that it will be useful but
17 * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
18 * DISCLAIMED. This includes but is not limited to warranties of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
20 *
21 */
22
23#ifndef __PARALLEL_H
24#define __PARALLEL_H
25
26#if __GNUC__ >=3
27#pragma GCC system_header
28#endif
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#include "ntddk.h"
35#include "ntddpar.h"
36
37#define DD_PARALLEL_PORT_BASE_NAME "ParallelPort"
38#define DD_PARALLEL_PORT_BASE_NAME_U L"ParallelPort"
39
40#define IOCTL_INTERNAL_DESELECT_DEVICE \
41 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 24, METHOD_BUFFERED, FILE_ANY_ACCESS)
42#define IOCTL_INTERNAL_GET_MORE_PARALLEL_PORT_INFO \
43 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 17, METHOD_BUFFERED, FILE_ANY_ACCESS)
44#define IOCTL_INTERNAL_GET_PARALLEL_PNP_INFO \
45 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 21, METHOD_BUFFERED, FILE_ANY_ACCESS)
46#define IOCTL_INTERNAL_GET_PARALLEL_PORT_INFO \
47 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 12, METHOD_BUFFERED, FILE_ANY_ACCESS)
48#define IOCTL_INTERNAL_INIT_1284_3_BUS \
49 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 22, METHOD_BUFFERED, FILE_ANY_ACCESS)
50#define IOCTL_INTERNAL_PARALLEL_CLEAR_CHIP_MODE \
51 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 20, METHOD_BUFFERED, FILE_ANY_ACCESS)
52#define IOCTL_INTERNAL_PARALLEL_CONNECT_INTERRUPT \
53 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 13, METHOD_BUFFERED, FILE_ANY_ACCESS)
54#define IOCTL_INTERNAL_PARALLEL_DISCONNECT_INTERRUPT \
55 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 14, METHOD_BUFFERED, FILE_ANY_ACCESS)
56#define IOCTL_INTERNAL_PARALLEL_PORT_ALLOCATE \
57 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 11, METHOD_BUFFERED, FILE_ANY_ACCESS)
58#define IOCTL_INTERNAL_PARALLEL_PORT_FREE \
59 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 40, METHOD_BUFFERED, FILE_ANY_ACCESS)
60#define IOCTL_INTERNAL_PARALLEL_SET_CHIP_MODE \
61 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 19, METHOD_BUFFERED, FILE_ANY_ACCESS)
62#define IOCTL_INTERNAL_RELEASE_PARALLEL_PORT_INFO \
63 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 15, METHOD_BUFFERED, FILE_ANY_ACCESS)
64#define IOCTL_INTERNAL_SELECT_DEVICE \
65 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 23, METHOD_BUFFERED, FILE_ANY_ACCESS)
66
67
68typedef struct _PARALLEL_1284_COMMAND {
69 UCHAR ID;
70 UCHAR Port;
71 ULONG CommandFlags;
72} PARALLEL_1284_COMMAND, *PPARALLEL_1284_COMMAND;
73
74/* PARALLEL_1284_COMMAND.CommandFlags */
75#define PAR_END_OF_CHAIN_DEVICE 0x00000001
76#define PAR_HAVE_PORT_KEEP_PORT 0x00000002
77
78typedef struct _MORE_PARALLEL_PORT_INFORMATION {
79 INTERFACE_TYPE InterfaceType;
80 ULONG BusNumber;
81 ULONG InterruptLevel;
82 ULONG InterruptVector;
83 KAFFINITY InterruptAffinity;
84 KINTERRUPT_MODE InterruptMode;
85} MORE_PARALLEL_PORT_INFORMATION, *PMORE_PARALLEL_PORT_INFORMATION;
86
87typedef NTSTATUS DDKAPI
88(*PPARALLEL_SET_CHIP_MODE)(
89 /*IN*/ PVOID SetChipContext,
90 /*IN*/ UCHAR ChipMode);
91
92typedef NTSTATUS DDKAPI
93(*PPARALLEL_CLEAR_CHIP_MODE)(
94 /*IN*/ PVOID ClearChipContext,
95 /*IN*/ UCHAR ChipMode);
96
97typedef NTSTATUS DDKAPI
98(*PPARCHIP_CLEAR_CHIP_MODE)(
99 /*IN*/ PVOID ClearChipContext,
100 /*IN*/ UCHAR ChipMode);
101
102typedef NTSTATUS DDKAPI
103(*PPARALLEL_TRY_SELECT_ROUTINE)(
104 /*IN*/ PVOID TrySelectContext,
105 /*IN*/ PVOID TrySelectCommand);
106
107typedef NTSTATUS DDKAPI
108(*PPARALLEL_DESELECT_ROUTINE)(
109 /*IN*/ PVOID DeselectContext,
110 /*IN*/ PVOID DeselectCommand);
111
112/* PARALLEL_PNP_INFORMATION.HardwareCapabilities */
113#define PPT_NO_HARDWARE_PRESENT 0x00000000
114#define PPT_ECP_PRESENT 0x00000001
115#define PPT_EPP_PRESENT 0x00000002
116#define PPT_EPP_32_PRESENT 0x00000004
117#define PPT_BYTE_PRESENT 0x00000008
118#define PPT_BIDI_PRESENT 0x00000008
119#define PPT_1284_3_PRESENT 0x00000010
120
121typedef struct _PARALLEL_PNP_INFORMATION {
122 PHYSICAL_ADDRESS OriginalEcpController;
123 PUCHAR EcpController;
124 ULONG SpanOfEcpController;
125 ULONG PortNumber;
126 ULONG HardwareCapabilities;
127 PPARALLEL_SET_CHIP_MODE TrySetChipMode;
128 PPARALLEL_CLEAR_CHIP_MODE ClearChipMode;
129 ULONG FifoDepth;
130 ULONG FifoWidth;
131 PHYSICAL_ADDRESS EppControllerPhysicalAddress;
132 ULONG SpanOfEppController;
133 ULONG Ieee1284_3DeviceCount;
134 PPARALLEL_TRY_SELECT_ROUTINE TrySelectDevice;
135 PPARALLEL_DESELECT_ROUTINE DeselectDevice;
136 PVOID Context;
137 ULONG CurrentMode;
138 PWSTR PortName;
139} PARALLEL_PNP_INFORMATION, *PPARALLEL_PNP_INFORMATION;
140
141typedef BOOLEAN DDKAPI
142(*PPARALLEL_TRY_ALLOCATE_ROUTINE)(
143 /*IN*/ PVOID TryAllocateContext);
144
145typedef VOID DDKAPI
146(*PPARALLEL_FREE_ROUTINE)(
147 /*IN*/ PVOID FreeContext);
148
149typedef ULONG DDKAPI
150(*PPARALLEL_QUERY_WAITERS_ROUTINE)(
151 /*IN*/ PVOID QueryAllocsContext);
152
153typedef struct _PARALLEL_PORT_INFORMATION {
154 PHYSICAL_ADDRESS OriginalController;
155 PUCHAR Controller;
156 ULONG SpanOfController;
157 PPARALLEL_TRY_ALLOCATE_ROUTINE TryAllocatePort;
158 PPARALLEL_FREE_ROUTINE FreePort;
159 PPARALLEL_QUERY_WAITERS_ROUTINE QueryNumWaiters;
160 PVOID Context;
161} PARALLEL_PORT_INFORMATION, *PPARALLEL_PORT_INFORMATION;
162
163/* PARALLEL_CHIP_MODE.ModeFlags */
164#define INITIAL_MODE 0x00
165#define PARCHIP_ECR_ARBITRATOR 0x01
166
167typedef struct _PARALLEL_CHIP_MODE {
168 UCHAR ModeFlags;
169 BOOLEAN success;
170} PARALLEL_CHIP_MODE, *PPARALLEL_CHIP_MODE;
171
172typedef VOID DDKAPI
173(*PPARALLEL_DEFERRED_ROUTINE)(
174 /*IN*/ PVOID DeferredContext);
175
176typedef struct _PARALLEL_INTERRUPT_SERVICE_ROUTINE {
177 PKSERVICE_ROUTINE InterruptServiceRoutine;
178 PVOID InterruptServiceContext;
179 PPARALLEL_DEFERRED_ROUTINE DeferredPortCheckRoutine;
180 PVOID DeferredPortCheckContext;
181} PARALLEL_INTERRUPT_SERVICE_ROUTINE, *PPARALLEL_INTERRUPT_SERVICE_ROUTINE;
182
183
184#define IOCTL_INTERNAL_DISCONNECT_IDLE \
185 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 32, METHOD_BUFFERED, FILE_ANY_ACCESS)
186#define IOCTL_INTERNAL_LOCK_PORT \
187 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 37, METHOD_BUFFERED, FILE_ANY_ACCESS)
188#define IOCTL_INTERNAL_LOCK_PORT_NO_SELECT \
189 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 52, METHOD_BUFFERED, FILE_ANY_ACCESS)
190#define IOCTL_INTERNAL_PARCLASS_CONNECT \
191 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 30, METHOD_BUFFERED, FILE_ANY_ACCESS)
192#define IOCTL_INTERNAL_PARCLASS_DISCONNECT \
193 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 31, METHOD_BUFFERED, FILE_ANY_ACCESS)
194#define IOCTL_INTERNAL_UNLOCK_PORT \
195 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 38, METHOD_BUFFERED, FILE_ANY_ACCESS)
196#define IOCTL_INTERNAL_UNLOCK_PORT_NO_DESELECT \
197 CTL_CODE (FILE_DEVICE_PARALLEL_PORT, 53, METHOD_BUFFERED, FILE_ANY_ACCESS)
198
199typedef USHORT DDKAPI
200(*PDETERMINE_IEEE_MODES)(
201 /*IN*/ PVOID Context);
202
203typedef enum _PARALLEL_SAFETY {
204 SAFE_MODE,
205 UNSAFE_MODE
206} PARALLEL_SAFETY;
207
208typedef NTSTATUS DDKAPI
209(*PNEGOTIATE_IEEE_MODE)(
210 /*IN*/ PVOID Context,
211 /*IN*/ USHORT ModeMaskFwd,
212 /*IN*/ USHORT ModeMaskRev,
213 /*IN*/ PARALLEL_SAFETY ModeSafety,
214 /*IN*/ BOOLEAN IsForward);
215
216typedef NTSTATUS DDKAPI
217(*PTERMINATE_IEEE_MODE)(
218 /*IN*/ PVOID Context);
219
220typedef NTSTATUS DDKAPI
221(*PPARALLEL_IEEE_FWD_TO_REV)(
222 /*IN*/ PVOID Context);
223
224typedef NTSTATUS DDKAPI
225(*PPARALLEL_IEEE_REV_TO_FWD)(
226 /*IN*/ PVOID Context);
227
228typedef NTSTATUS DDKAPI
229(*PPARALLEL_READ)(
230 /*IN*/ PVOID Context,
231 /*OUT*/ PVOID Buffer,
232 /*IN*/ ULONG NumBytesToRead,
233 /*OUT*/ PULONG NumBytesRead,
234 /*IN*/ UCHAR Channel);
235
236typedef NTSTATUS DDKAPI
237(*PPARALLEL_WRITE)(
238 /*IN*/ PVOID Context,
239 /*OUT*/ PVOID Buffer,
240 /*IN*/ ULONG NumBytesToWrite,
241 /*OUT*/ PULONG NumBytesWritten,
242 /*IN*/ UCHAR Channel);
243
244typedef NTSTATUS DDKAPI
245(*PPARALLEL_TRYSELECT_DEVICE)(
246 /*IN*/ PVOID Context,
247 /*IN*/ PARALLEL_1284_COMMAND Command);
248
249typedef NTSTATUS DDKAPI
250(*PPARALLEL_DESELECT_DEVICE)(
251 /*IN*/ PVOID Context,
252 /*IN*/ PARALLEL_1284_COMMAND Command);
253
254typedef struct _PARCLASS_INFORMATION {
255 PUCHAR Controller;
256 PUCHAR EcrController;
257 ULONG SpanOfController;
258 PDETERMINE_IEEE_MODES DetermineIeeeModes;
259 PNEGOTIATE_IEEE_MODE NegotiateIeeeMode;
260 PTERMINATE_IEEE_MODE TerminateIeeeMode;
261 PPARALLEL_IEEE_FWD_TO_REV IeeeFwdToRevMode;
262 PPARALLEL_IEEE_REV_TO_FWD IeeeRevToFwdMode;
263 PPARALLEL_READ ParallelRead;
264 PPARALLEL_WRITE ParallelWrite;
265 PVOID ParclassContext;
266 ULONG HardwareCapabilities;
267 ULONG FifoDepth;
268 ULONG FifoWidth;
269 PPARALLEL_TRYSELECT_DEVICE ParallelTryselect;
270 PPARALLEL_DESELECT_DEVICE ParallelDeSelect;
271} PARCLASS_INFORMATION, *PPARCLASS_INFORMATION;
272
273#ifdef __cplusplus
274}
275#endif
276
277#endif /* __PARALLEL_H */
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