source: Daodan/MinGW/lib/gcc/mingw32/5.3.0/include/cpuid.h@ 1117

Last change on this file since 1117 was 1046, checked in by alloc, 8 years ago

Daodan: Added Windows MinGW and build batch file
File size: 7.0 KB
Line 
1/*
2 * Copyright (C) 2007-2015 Free Software Foundation, Inc.
3 *
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 3, or (at your option) any
7 * later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * Under Section 7 of GPL version 3, you are granted additional
15 * permissions described in the GCC Runtime Library Exception, version
16 * 3.1, as published by the Free Software Foundation.
17 *
18 * You should have received a copy of the GNU General Public License and
19 * a copy of the GCC Runtime Library Exception along with this program;
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 * <http://www.gnu.org/licenses/>.
22 */
23
24/* %ecx */
25#define bit_SSE3 (1 << 0)
26#define bit_PCLMUL (1 << 1)
27#define bit_LZCNT (1 << 5)
28#define bit_SSSE3 (1 << 9)
29#define bit_FMA (1 << 12)
30#define bit_CMPXCHG16B (1 << 13)
31#define bit_SSE4_1 (1 << 19)
32#define bit_SSE4_2 (1 << 20)
33#define bit_MOVBE (1 << 22)
34#define bit_POPCNT (1 << 23)
35#define bit_AES (1 << 25)
36#define bit_XSAVE (1 << 26)
37#define bit_OSXSAVE (1 << 27)
38#define bit_AVX (1 << 28)
39#define bit_F16C (1 << 29)
40#define bit_RDRND (1 << 30)
41
42/* %edx */
43#define bit_CMPXCHG8B (1 << 8)
44#define bit_CMOV (1 << 15)
45#define bit_MMX (1 << 23)
46#define bit_FXSAVE (1 << 24)
47#define bit_SSE (1 << 25)
48#define bit_SSE2 (1 << 26)
49
50/* Extended Features */
51/* %ecx */
52#define bit_LAHF_LM (1 << 0)
53#define bit_ABM (1 << 5)
54#define bit_SSE4a (1 << 6)
55#define bit_PRFCHW (1 << 8)
56#define bit_XOP (1 << 11)
57#define bit_LWP (1 << 15)
58#define bit_FMA4 (1 << 16)
59#define bit_TBM (1 << 21)
60#define bit_MWAITX (1 << 29)
61
62/* %edx */
63#define bit_MMXEXT (1 << 22)
64#define bit_LM (1 << 29)
65#define bit_3DNOWP (1 << 30)
66#define bit_3DNOW (1 << 31)
67
68/* Extended Features (%eax == 7) */
69/* %ebx */
70#define bit_FSGSBASE (1 << 0)
71#define bit_BMI (1 << 3)
72#define bit_HLE (1 << 4)
73#define bit_AVX2 (1 << 5)
74#define bit_BMI2 (1 << 8)
75#define bit_RTM (1 << 11)
76#define bit_MPX (1 << 14)
77#define bit_AVX512F (1 << 16)
78#define bit_AVX512DQ (1 << 17)
79#define bit_RDSEED (1 << 18)
80#define bit_ADX (1 << 19)
81#define bit_AVX512IFMA (1 << 21)
82#define bit_PCOMMIT (1 << 22)
83#define bit_CLFLUSHOPT (1 << 23)
84#define bit_CLWB (1 << 24)
85#define bit_AVX512PF (1 << 26)
86#define bit_AVX512ER (1 << 27)
87#define bit_AVX512CD (1 << 28)
88#define bit_SHA (1 << 29)
89#define bit_AVX512BW (1 << 30)
90#define bit_AVX512VL (1 << 31)
91
92/* %ecx */
93#define bit_PREFETCHWT1 (1 << 0)
94#define bit_AVX512VBMI (1 << 1)
95
96/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
97#define bit_BNDREGS (1 << 3)
98#define bit_BNDCSR (1 << 4)
99
100/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
101#define bit_XSAVEOPT (1 << 0)
102#define bit_XSAVEC (1 << 1)
103#define bit_XSAVES (1 << 3)
104
105/* Signatures for different CPU implementations as returned in uses
106 of cpuid with level 0. */
107#define signature_AMD_ebx 0x68747541
108#define signature_AMD_ecx 0x444d4163
109#define signature_AMD_edx 0x69746e65
110
111#define signature_CENTAUR_ebx 0x746e6543
112#define signature_CENTAUR_ecx 0x736c7561
113#define signature_CENTAUR_edx 0x48727561
114
115#define signature_CYRIX_ebx 0x69727943
116#define signature_CYRIX_ecx 0x64616574
117#define signature_CYRIX_edx 0x736e4978
118
119#define signature_INTEL_ebx 0x756e6547
120#define signature_INTEL_ecx 0x6c65746e
121#define signature_INTEL_edx 0x49656e69
122
123#define signature_TM1_ebx 0x6e617254
124#define signature_TM1_ecx 0x55504361
125#define signature_TM1_edx 0x74656d73
126
127#define signature_TM2_ebx 0x756e6547
128#define signature_TM2_ecx 0x3638784d
129#define signature_TM2_edx 0x54656e69
130
131#define signature_NSC_ebx 0x646f6547
132#define signature_NSC_ecx 0x43534e20
133#define signature_NSC_edx 0x79622065
134
135#define signature_NEXGEN_ebx 0x4778654e
136#define signature_NEXGEN_ecx 0x6e657669
137#define signature_NEXGEN_edx 0x72446e65
138
139#define signature_RISE_ebx 0x65736952
140#define signature_RISE_ecx 0x65736952
141#define signature_RISE_edx 0x65736952
142
143#define signature_SIS_ebx 0x20536953
144#define signature_SIS_ecx 0x20536953
145#define signature_SIS_edx 0x20536953
146
147#define signature_UMC_ebx 0x20434d55
148#define signature_UMC_ecx 0x20434d55
149#define signature_UMC_edx 0x20434d55
150
151#define signature_VIA_ebx 0x20414956
152#define signature_VIA_ecx 0x20414956
153#define signature_VIA_edx 0x20414956
154
155#define signature_VORTEX_ebx 0x74726f56
156#define signature_VORTEX_ecx 0x436f5320
157#define signature_VORTEX_edx 0x36387865
158
159#define __cpuid(level, a, b, c, d) \
160 __asm__ ("cpuid\n\t" \
161 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
162 : "0" (level))
163
164#define __cpuid_count(level, count, a, b, c, d) \
165 __asm__ ("cpuid\n\t" \
166 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
167 : "0" (level), "2" (count))
168
169
170/* Return highest supported input value for cpuid instruction. ext can
171 be either 0x0 or 0x8000000 to return highest supported value for
172 basic or extended cpuid information. Function returns 0 if cpuid
173 is not supported or whatever cpuid returns in eax register. If sig
174 pointer is non-null, then first four bytes of the signature
175 (as found in ebx register) are returned in location pointed by sig. */
176
177static __inline unsigned int
178__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
179{
180 unsigned int __eax, __ebx, __ecx, __edx;
181
182#ifndef __x86_64__
183 /* See if we can use cpuid. On AMD64 we always can. */
184#if __GNUC__ >= 3
185 __asm__ ("pushf{l|d}\n\t"
186 "pushf{l|d}\n\t"
187 "pop{l}\t%0\n\t"
188 "mov{l}\t{%0, %1|%1, %0}\n\t"
189 "xor{l}\t{%2, %0|%0, %2}\n\t"
190 "push{l}\t%0\n\t"
191 "popf{l|d}\n\t"
192 "pushf{l|d}\n\t"
193 "pop{l}\t%0\n\t"
194 "popf{l|d}\n\t"
195 : "=&r" (__eax), "=&r" (__ebx)
196 : "i" (0x00200000));
197#else
198/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
199 nor alternatives in i386 code. */
200 __asm__ ("pushfl\n\t"
201 "pushfl\n\t"
202 "popl\t%0\n\t"
203 "movl\t%0, %1\n\t"
204 "xorl\t%2, %0\n\t"
205 "pushl\t%0\n\t"
206 "popfl\n\t"
207 "pushfl\n\t"
208 "popl\t%0\n\t"
209 "popfl\n\t"
210 : "=&r" (__eax), "=&r" (__ebx)
211 : "i" (0x00200000));
212#endif
213
214 if (!((__eax ^ __ebx) & 0x00200000))
215 return 0;
216#endif
217
218 /* Host supports cpuid. Return highest supported cpuid input value. */
219 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
220
221 if (__sig)
222 *__sig = __ebx;
223
224 return __eax;
225}
226
227/* Return cpuid data for requested cpuid level, as found in returned
228 eax, ebx, ecx and edx registers. The function checks if cpuid is
229 supported and returns 1 for valid cpuid information or 0 for
230 unsupported cpuid level. All pointers are required to be non-null. */
231
232static __inline int
233__get_cpuid (unsigned int __level,
234 unsigned int *__eax, unsigned int *__ebx,
235 unsigned int *__ecx, unsigned int *__edx)
236{
237 unsigned int __ext = __level & 0x80000000;
238
239 if (__get_cpuid_max (__ext, 0) < __level)
240 return 0;
241
242 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
243 return 1;
244}
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