source: Daodan/src/beaengine/Includes/internal_datas.h

Last change on this file was 984, checked in by alloc, 11 years ago

Daodan: TV code
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1/* Copyright 2006-2009, BeatriX
2 * File coded by BeatriX
3 *
4 * This file is part of BeaEngine.
5 *
6 * BeaEngine is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * BeaEngine is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with BeaEngine. If not, see <http://www.gnu.org/licenses/>. */
18
19/* Define prefix GV aka GlobalVariable - used instead of global internal variables to make BeaEngine thread-safe */
20
21#define GV (*pMyDisasm).Reserved_
22
23/* Define constants to identify the position and type of decoration used in case of memory argument */
24
25#define Arg1byte 1
26#define Arg1word 2
27#define Arg1dword 3
28#define Arg1qword 4
29#define Arg1multibytes 5
30#define Arg1tbyte 6
31#define Arg1fword 7
32#define Arg1dqword 8
33
34#define Arg2byte 101
35#define Arg2word 102
36#define Arg2dword 103
37#define Arg2qword 104
38#define Arg2multibytes 105
39#define Arg2tbyte 106
40#define Arg2fword 107
41#define Arg2dqword 108
42
43EFLStruct EFLAGS_TABLE[] = {
44 {UN_, UN_, UN_, MO_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 0-AAA */
45 {UN_, MO_, MO_, UN_, MO_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 1-AAD */
46 {UN_, MO_, MO_, UN_, MO_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 2-AAM */
47 {UN_, UN_, UN_, MO_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 3-AAS */
48 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 4-ADC */
49 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 5-ADD */
50 {RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 6-AND */
51 {0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 7-ARPL */
52 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 8-BOUND */
53 {UN_, UN_, MO_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 9-BSF/BSR */
54
55 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 10-BSWAP */
56 {UN_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 11-BT/BTS/BTR/BTC */
57 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 12-CALL */
58 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 13-CBW */
59 {0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 14-CLC */
60 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0, 0}, /* 15-CLD */
61 {0 , 0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , 0, 0}, /* 16-CLI */
62 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 17-CLTS */
63 {0 , 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 18-CMC */
64 {TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 19-CMOVcc */
65
66 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 20-CMP */
67 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 21-CMPS */
68 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 22-CMPXCHG */
69 {0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 23-CMPXCHGG8B */
70 {RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 24-COMSID */
71 {RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 25-COMISS */
72 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 26-CPUID */
73 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 27-CWD */
74 {UN_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 28-DAA */
75 {UN_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 29-DAS */
76
77 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 30-DEC */
78 {UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 31-DIV */
79 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 32-ENTER */
80 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 33-ESC */
81 {0 , 0 , TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 34-FCMOV */
82 {0 , 0 , MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 35-FCOMI FCOMIP FUCMI FUCMIP */
83 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 36-HLT */
84 {UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 37-IDIV */
85 {MO_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 38-IMUL */
86 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 39-IN */
87
88 {MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 40-INC */
89 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 41-INS */
90 {0 , 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , RE_, 0, 0}, /* 42-INT */
91 {TE_, 0 , 0 , 0 , 0 , 0 , RE_, 0 , 0 , RE_, 0, 0}, /* 43-INTO */
92 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 44-INVD */
93 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 45-INVLPG */
94 {RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 46-UCOMSID */
95 {RE_, RE_, MO_, RE_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 47-UCOMISS */
96 {PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, TE_, 0, 0}, /* 48-IRET */
97 {TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 49-Jcc */
98
99 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 50-JCXZ */
100 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 51-JMP */
101 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 52-LAHF */
102 {0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 53-LAR */
103 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 54-LDS LES LSS LFS LGS */
104 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 55-LEA */
105 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 56-LEAVE */
106 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 57-LGDT LIDT LLDT LMSW */
107 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 58-LOCK */
108 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 59-LODS */
109
110 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 60-LOOP */
111 {0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 61-LOOPE LOOPNE */
112 {0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 62-LSL */
113 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 63-LTR */
114 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 64-MONITOR */
115 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 65-MWAIT */
116 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 66-MOV */
117 {UN_, UN_, UN_, UN_, UN_, UN_, 0 , 0 , 0 , 0 , 0, 0}, /* 67-MOV control, debug, test */
118 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 68-MOVS */
119 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 69-MOVSX MOVZX */
120
121 {MO_, UN_, UN_, UN_, UN_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 70-MUL */
122 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 71-NEG */
123 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 72-NOP */
124 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 73-NOT */
125 {RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 74-OR */
126 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 75-OUT */
127 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , TE_, 0 , 0, 0}, /* 76-OUTS */
128 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 77-POP POPA */
129 {PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, PR_, 0, 0}, /* 78-POPF */
130 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 79-PUSH PUSHA PUSHF */
131
132 {MO_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 80-RCL RCR 1 */
133 {UN_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 81-RCL RCR */
134 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 82-RDMSR */
135 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 83-RDPMC */
136 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 84-RDTSC */
137 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 85-REP REPE REPNE */
138 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 86-RET */
139 {MO_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 87-ROL ROR 1 */
140 {UN_, 0 , 0 , 0 , 0 , MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 88-ROL ROR */
141 {MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, MO_, 0}, /* 89-RSM */
142
143 {0 , PR_, PR_, PR_, PR_, PR_, 0 , 0 , 0 , 0 , 0, 0}, /* 90-SAHF */
144 {MO_, MO_, MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 91-SAL SAR SHL SHR 1 */
145 {0 , MO_, MO_, 0 , MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 92-SAL SAR SHL SHR */
146 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 93-SBB */
147 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 94-SCAS */
148 {TE_, TE_, TE_, 0 , TE_, TE_, 0 , 0 , 0 , 0 , 0, 0}, /* 95-SETcc */
149 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 96-SGDT SIDT SLDT SMSW */
150 {UN_, MO_, MO_, UN_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 97-SHLD SHRD */
151 {0 , 0 , 0 , 0 , 0 , SE_, 0 , 0 , 0 , 0 , 0, 0}, /* 98-STC */
152 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , SE_, 0 , 0, 0}, /* 99-STD */
153
154 {0 , 0 , 0 , 0 , 0 , 0 , 0 , SE_, 0 , 0 , 0, 0}, /* 100-STI */
155 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 101-STOS */
156 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 102-STR */
157 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 103-SUB */
158 {RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 104-TEST */
159 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 105-UD2 */
160 {0 , 0 , MO_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 106-VERR VERRW */
161 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 107-WAIT */
162 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 108-WBINVD */
163 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 109-WRMSR */
164
165 {MO_, MO_, MO_, MO_, MO_, MO_, 0 , 0 , 0 , 0 , 0, 0}, /* 110-XADD */
166 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 111-XCHG */
167 {0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 112-XLAT */
168 {RE_, MO_, MO_, UN_, MO_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 113-XOR */
169
170 {RE_, RE_, MO_, RE_, RE_, RE_, 0 , 0 , 0 , 0 , 0, 0}, /* 114-POPCNT */
171
172 {TE_, TE_, TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*115 -jg jnle jng jle http://ref.x86asm.net/coder.html */
173 {TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*116 -jo jno http://ref.x86asm.net/coder.html */
174 {0 , 0 , 0 , 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0, 0}, /*117 -jc jnc jb jnb jnae jae http://ref.x86asm.net/coder.html */
175 {0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /*118 -jz jnz je jne http://ref.x86asm.net/coder.html */
176 {0 , 0 , TE_, 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0, 0}, /*119 -jbe jnbe jna ja http://ref.x86asm.net/coder.html */
177
178 {0 , TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 120 - js jns http://ref.x86asm.net/coder.html */
179 {0 , 0 , 0 , 0 , TE_, 0 , 0 , 0 , 0 , 0 , 0, 0}, /* 121 - jp jpe jnp jpo http://ref.x86asm.net/coder.html */
180 {TE_, TE_, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, 0} /* 122 - jl jnge jnl jge http://ref.x86asm.net/coder.html */
181
182 };
183/* =====================================================
184 * To make a tabulation between mnemonic and first argument
185 * ===================================================== */
186char space_tab[11][16] = {
187 " ",
188 " ",
189 " ",
190 " ",
191 " ",
192 " ",
193 " ",
194 " ",
195 " ",
196 " ",
197 " ",
198
199};
200/* =====================================================
201 * Segment registers
202 * ===================================================== */
203char SegmentRegs[7][4] = {
204 "??:", /* +0 */
205 "es:", /* +1 */
206 "ds:", /* +2 */
207 "fs:", /* +3 */
208 "gs:", /* +4 */
209 "cs:", /* +5 */
210 "ss:", /* +6 */
211};
212/* =====================================================
213 * AT&T Suffixes
214 * ===================================================== */
215char ATSuffixes[8][4] = {
216 "b ", /* GV.MemDecoration == 1 */
217 "w ", /* GV.MemDecoration == 2 */
218 "l ", /* GV.MemDecoration == 3 */
219 "q ", /* GV.MemDecoration == 4 */
220 " ", /* GV.MemDecoration == 5 (multibytes) */
221 "t ", /* GV.MemDecoration == 6 */
222 " ", /* GV.MemDecoration == 7 (fword) */
223 " ", /* GV.MemDecoration == 8 (dqword) */
224};
225
226/* =====================================================
227 * MASM Prefixes for MemoryType
228 * ===================================================== */
229
230char MasmPrefixes[8][16] = {
231 "byte ptr ", /* GV.MemDecoration == 1 */
232 "word ptr ", /* GV.MemDecoration == 2 */
233 "dword ptr ", /* GV.MemDecoration == 3 */
234 "qword ptr ", /* GV.MemDecoration == 4 */
235 " ", /* GV.MemDecoration == 5 (multibytes) */
236 "tbyte ptr ", /* GV.MemDecoration == 6 */
237 "fword ptr ", /* GV.MemDecoration == 7 (fword) */
238 "dqword ptr ", /* GV.MemDecoration == 8 (dqword) */
239};
240
241/* =====================================================
242 * NASM Prefixes for MemoryType
243 * ===================================================== */
244char NasmPrefixes[8][8] = {
245 "byte ", /* GV.MemDecoration == 1 */
246 "word ", /* GV.MemDecoration == 2 */
247 " ", /* GV.MemDecoration == 3 */
248 "qword ", /* GV.MemDecoration == 4 */
249 " ", /* GV.MemDecoration == 5 (multibytes) */
250 "tword ", /* GV.MemDecoration == 6 */
251 " ", /* GV.MemDecoration == 7 (fword) */
252 " ", /* GV.MemDecoration == 8 (dqword) */
253};
254
255
256
257/* =====================================================
258 * GOASM Prefixes for MemoryType
259 * ===================================================== */
260char GoAsmPrefixes[8][4] = {
261 "b ", /* GV.MemDecoration == 1 */
262 "w ", /* GV.MemDecoration == 2 */
263 "d ", /* GV.MemDecoration == 3 */
264 "q ", /* GV.MemDecoration == 4 */
265 " ", /* GV.MemDecoration == 5 (multibytes) */
266 "t ", /* GV.MemDecoration == 6 */
267 " ", /* GV.MemDecoration == 7 (fword) */
268 " ", /* GV.MemDecoration == 8 (dqword) */
269};
270
271
272/* =====================================================
273 * Segment registers
274 * ===================================================== */
275char RegistersSEG[16][8] = {
276 "es", /* +0 */
277 "cs", /* +1 */
278 "ss", /* +2 */
279 "ds", /* +3 */
280 "fs", /* +4 */
281 "gs", /* +5 */
282 "seg?",
283 "seg?",
284 "seg?",
285 "seg?",
286 "seg?",
287 "seg?",
288 "seg?",
289 "seg?",
290 "seg?",
291 "seg?",
292};
293
294/* =====================================================
295 * FPU Registers
296 * ===================================================== */
297char RegistersFPU_Masm[8][8] = {
298 "st(0)", /* +0 */
299 "st(1)", /* +1 */
300 "st(2)", /* +2 */
301 "st(3)", /* +3 */
302 "st(4)", /* +4 */
303 "st(5)", /* +5 */
304 "st(6)", /* +6 */
305 "st(7)", /* +7 */
306};
307
308char RegistersFPU_Nasm[8][8] = {
309 "st0", /* +0 */
310 "st1", /* +1 */
311 "st2", /* +2 */
312 "st3", /* +3 */
313 "st4", /* +4 */
314 "st5", /* +5 */
315 "st6", /* +6 */
316 "st7", /* +7 */
317};
318
319/* =====================================================
320 * debug registers
321 * ===================================================== */
322char RegistersDR[16][8] = {
323 "dr0", /* +0 */
324 "dr1", /* +1 */
325 "dr2", /* +2 */
326 "dr3", /* +3 */
327 "dr4", /* +4 */
328 "dr5", /* +5 */
329 "dr6", /* +6 */
330 "dr7", /* +7 */
331 "dr8", /* +8 */
332 "dr9", /* +9 */
333 "dr10", /* +10 */
334 "dr11", /* +11 */
335 "dr12", /* +12 */
336 "dr13", /* +13 */
337 "dr14", /* +14 */
338 "dr15", /* +15 */
339};
340
341/* =====================================================
342 * debug registers-AT&T syntax
343 * ===================================================== */
344char RegistersDR_AT[16][8] = {
345 "db0", /* +0 */
346 "db1", /* +1 */
347 "db2", /* +2 */
348 "db3", /* +3 */
349 "db4", /* +4 */
350 "db5", /* +5 */
351 "db6", /* +6 */
352 "db7", /* +7 */
353 "db8", /* +8 */
354 "db9", /* +9 */
355 "db10", /* +10 */
356 "db11", /* +11 */
357 "db12", /* +12 */
358 "db13", /* +13 */
359 "db14", /* +14 */
360 "db15", /* +15 */
361};
362
363
364/* =====================================================
365 * control registers
366 * ===================================================== */
367char RegistersCR[16][8] = {
368 "cr0", /* +0 */
369 "cr1", /* +1 */
370 "cr2", /* +2 */
371 "cr3", /* +3 */
372 "cr4", /* +4 */
373 "cr5", /* +5 */
374 "cr6", /* +6 */
375 "cr7", /* +7 */
376 "cr8", /* +8 */
377 "cr9", /* +9 */
378 "cr10", /* +10 */
379 "cr11", /* +11 */
380 "cr12", /* +12 */
381 "cr13", /* +13 */
382 "cr14", /* +14 */
383 "cr15", /* +15 */
384};
385
386
387
388/* =====================================================
389 * 64 bits registers
390 * ===================================================== */
391char Registers64Bits[16][4] = {
392 "rax", /* +0 */
393 "rcx", /* +1 */
394 "rdx", /* +2 */
395 "rbx", /* +3 */
396 "rsp", /* +4 */
397 "rbp", /* +5 */
398 "rsi", /* +6 */
399 "rdi", /* +7 */
400 "r8", /* +8 */
401 "r9", /* +9 */
402 "r10", /* +10 */
403 "r11", /* +11 */
404 "r12", /* +12 */
405 "r13", /* +13 */
406 "r14", /* +14 */
407 "r15", /* +15 */
408};
409
410/* =====================================================
411 * 32 bits registers
412 * ===================================================== */
413char Registers32Bits[16][8] = {
414 "eax",
415 "ecx",
416 "edx",
417 "ebx",
418 "esp",
419 "ebp",
420 "esi",
421 "edi",
422 "r8d",
423 "r9d",
424 "r10d",
425 "r11d",
426 "r12d",
427 "r13d",
428 "r14d",
429 "r15d",
430};
431
432/* =====================================================
433 * 16 bits registers
434 * ===================================================== */
435char Registers16Bits[16][8] = {
436 "ax",
437 "cx",
438 "dx",
439 "bx",
440 "sp",
441 "bp",
442 "si",
443 "di",
444 "r8w",
445 "r9w",
446 "r10w",
447 "r11w",
448 "r12w",
449 "r13w",
450 "r14w",
451 "r15w",
452};
453/* =====================================================
454 * 8 bits registers
455 * ===================================================== */
456char Registers8BitsLegacy[8][4] = {
457 "al",
458 "cl",
459 "dl",
460 "bl",
461 "ah",
462 "ch",
463 "dh",
464 "bh",
465};
466
467Int32 REGS8BITS[] = {
468 REG0,
469 REG1,
470 REG2,
471 REG3,
472 REG0,
473 REG1,
474 REG2,
475 REG3,
476};
477
478/* =====================================================
479 * 8 bits registers
480 * ===================================================== */
481char Registers8Bits[16][8] = {
482 "al",
483 "cl",
484 "dl",
485 "bl",
486 "spl",
487 "bpl",
488 "sil",
489 "dil",
490 "r8L",
491 "r9L",
492 "r10L",
493 "r11L",
494 "r12L",
495 "r13L",
496 "r14L",
497 "r15L",
498};
499/* =====================================================
500 * MMX Registers
501 * ===================================================== */
502char RegistersMMX[8][4] = {
503 "mm0",
504 "mm1",
505 "mm2",
506 "mm3",
507 "mm4",
508 "mm5",
509 "mm6",
510 "mm7",
511};
512
513/* =====================================================
514 * SSE Registers
515 * ===================================================== */
516char RegistersSSE[16][8] = {
517 "xmm0",
518 "xmm1",
519 "xmm2",
520 "xmm3",
521 "xmm4",
522 "xmm5",
523 "xmm6",
524 "xmm7",
525 "xmm8", /* SSE3, SSSE3, SSE4 */
526 "xmm9", /* SSE3, SSSE3, SSE4 */
527 "xmm10", /* SSE3, SSSE3, SSE4 */
528 "xmm11", /* SSE3, SSSE3, SSE4 */
529 "xmm12", /* SSE3, SSSE3, SSE4 */
530 "xmm13", /* SSE3, SSSE3, SSE4 */
531 "xmm14", /* SSE3, SSSE3, SSE4 */
532 "xmm15", /* SSE3, SSSE3, SSE4 */
533};
534
535Int32 REGS[] = {
536 REG0, /* REG0 */
537 REG1, /* REG1 */
538 REG2, /* REG2 */
539 REG3, /* REG3 */
540 REG4, /* REG4 */
541 REG5, /* REG5 */
542 REG6, /* REG6 */
543 REG7, /* REG7 */
544 REG8, /* REG8 */
545 REG9, /* REG9 */
546 REG10, /* REG10 */
547 REG11, /* REG11 */
548 REG12, /* REG12 */
549 REG13, /* REG13 */
550 REG14, /* REG14 */
551 REG15, /* REG15 */
552};
553
554char BXSI_[] = "bx+si";
555char BXDI_[] = "bx+di";
556char BPSI_[] = "bp+si";
557char BPDI_[] = "bp+di";
558
559
560
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