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* gcc: (gcc).                  The GNU Compiler Collection.
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   This file documents the use of the GNU compilers.

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File: gcc.info,  Node: ARM Options,  Next: MN10200 Options,  Prev: AMD29K Options,  Up: Submodel Options

ARM Options
-----------

   These `-m' options are defined for Advanced RISC Machines (ARM)
architectures:

`-mapcs-frame'
     Generate a stack frame that is compliant with the ARM Procedure
     Call Standard for all functions, even if this is not strictly
     necessary for correct execution of the code.  Specifying
     `-fomit-frame-pointer' with this option will cause the stack
     frames not to be generated for leaf functions.  The default is
     `-mno-apcs-frame'.

`-mapcs'
     This is a synonym for `-mapcs-frame'.

`-mapcs-26'
     Generate code for a processor running with a 26-bit program
     counter, and conforming to the function calling standards for the
     APCS 26-bit option.  This option replaces the `-m2' and `-m3'
     options of previous releases of the compiler.

`-mapcs-32'
     Generate code for a processor running with a 32-bit program
     counter, and conforming to the function calling standards for the
     APCS 32-bit option.  This option replaces the `-m6' option of
     previous releases of the compiler.

`-mthumb-interwork'
     Generate code which supports calling between the ARM and Thumb
     instruction sets.  Without this option the two instruction sets
     cannot be reliably used inside one program.  The default is
     `-mno-thumb-interwork', since slightly larger code is generated
     when `-mthumb-interwork' is specified.

`-mno-sched-prolog'
     Prevent the reordering of instructions in the function prolog, or
     the merging of those instruction with the instructions in the
     function's body.  This means that all functions will start with a
     recognizable set of instructions (or in fact one of a choice from
     a small set of different function prologues), and this information
     can be used to locate the start if functions inside an executable
     piece of code.  The default is `-msched-prolog'.

`-mhard-float'
     Generate output containing floating point instructions.  This is
     the default.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not available for all ARM
     targets.  Normally the facilities of the machine's usual C
     compiler are used, but this cannot be done directly in
     cross-compilation.  You must make your own arrangements to provide
     suitable library functions for cross-compilation.

     `-msoft-float' changes the calling convention in the output file;
     therefore, it is only useful if you compile _all_ of a program with
     this option.  In particular, you need to compile `libgcc.a', the
     library that comes with GCC, with `-msoft-float' in order for this
     to work.

`-mlittle-endian'
     Generate code for a processor running in little-endian mode.  This
     is the default for all standard configurations.

`-mbig-endian'
     Generate code for a processor running in big-endian mode; the
     default is to compile code for a little-endian processor.

`-mwords-little-endian'
     This option only applies when generating code for big-endian
     processors.  Generate code for a little-endian word order but a
     big-endian byte order.  That is, a byte order of the form
     `32107654'.  Note: this option should only be used if you require
     compatibility with code for big-endian ARM processors generated by
     versions of the compiler prior to 2.8.

`-malignment-traps'
     Generate code that will not trap if the MMU has alignment traps
     enabled.  On ARM architectures prior to ARMv4, there were no
     instructions to access half-word objects stored in memory.
     However, when reading from memory a feature of the ARM
     architecture allows a word load to be used, even if the address is
     unaligned, and the processor core will rotate the data as it is
     being loaded.  This option tells the compiler that such misaligned
     accesses will cause a MMU trap and that it should instead
     synthesise the access as a series of byte accesses.  The compiler
     can still use word accesses to load half-word data if it knows
     that the address is aligned to a word boundary.

     This option is ignored when compiling for ARM architecture 4 or
     later, since these processors have instructions to directly access
     half-word objects in memory.

`-mno-alignment-traps'
     Generate code that assumes that the MMU will not trap unaligned
     accesses.  This produces better code when the target instruction
     set does not have half-word memory operations (i.e.
     implementations prior to ARMv4).

     Note that you cannot use this option to access unaligned word
     objects, since the processor will only fetch one 32-bit aligned
     object from memory.

     The default setting for most targets is `-mno-alignment-traps',
     since this produces better code when there are no half-word memory
     instructions available.

`-mshort-load-bytes'
`-mno-short-load-words'
     These are deprecated aliases for `-malignment-traps'.

`-mno-short-load-bytes'
`-mshort-load-words'
     This are deprecated aliases for `-mno-alignment-traps'.

`-mbsd'
     This option only applies to RISC iX.  Emulate the native BSD-mode
     compiler.  This is the default if `-ansi' is not specified.

`-mxopen'
     This option only applies to RISC iX.  Emulate the native
     X/Open-mode compiler.

`-mno-symrename'
     This option only applies to RISC iX.  Do not run the assembler
     post-processor, `symrename', after code has been assembled.
     Normally it is necessary to modify some of the standard symbols in
     preparation for linking with the RISC iX C library; this option
     suppresses this pass.  The post-processor is never run when the
     compiler is built for cross-compilation.

`-mcpu=NAME'
     This specifies the name of the target ARM processor.  GCC uses
     this name to determine what kind of instructions it can emit when
     generating assembly code.  Permissible names are: `arm2', `arm250',
     `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
     `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
     `arm700i', `arm710', `arm710c', `arm7100', `arm7500', `arm7500fe',
     `arm7tdmi', `arm8', `strongarm', `strongarm110', `strongarm1100',
     `arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t', `arm940t',
     `arm9tdmi', `arm10tdmi', `arm1020t', `xscale'.

`-mtune=NAME'
     This option is very similar to the `-mcpu=' option, except that
     instead of specifying the actual target processor type, and hence
     restricting which instructions can be used, it specifies that GCC
     should tune the performance of the code as if the target were of
     the type specified in this option, but still choosing the
     instructions that it will generate based on the cpu specified by a
     `-mcpu=' option.  For some ARM implementations better performance
     can be obtained by using this option.

`-march=NAME'
     This specifies the name of the target ARM architecture.  GCC uses
     this name to determine what kind of instructions it can emit when
     generating assembly code.  This option can be used in conjunction
     with or instead of the `-mcpu=' option.  Permissible names are:
     `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5',
     `armv5t', `armv5te'.

`-mfpe=NUMBER'
`-mfp=NUMBER'
     This specifies the version of the floating point emulation
     available on the target.  Permissible values are 2 and 3.  `-mfp='
     is a synonym for `-mfpe=', for compatibility with older versions
     of GCC.

`-mstructure-size-boundary=N'
     The size of all structures and unions will be rounded up to a
     multiple of the number of bits set by this option.  Permissible
     values are 8 and 32.  The default value varies for different
     toolchains.  For the COFF targeted toolchain the default value is
     8.  Specifying the larger number can produce faster, more
     efficient code, but can also increase the size of the program.
     The two values are potentially incompatible.  Code compiled with
     one value cannot necessarily expect to work with code or libraries
     compiled with the other value, if they exchange information using
     structures or unions.

`-mabort-on-noreturn'
     Generate a call to the function `abort' at the end of a `noreturn'
     function.  It will be executed if the function tries to return.

`-mlong-calls'
`-mno-long-calls'
     Tells the compiler to perform function calls by first loading the
     address of the function into a register and then performing a
     subroutine call on this register.  This switch is needed if the
     target function will lie outside of the 64 megabyte addressing
     range of the offset based version of subroutine call instruction.

     Even if this switch is enabled, not all function calls will be
     turned into long calls.  The heuristic is that static functions,
     functions which have the `short-call' attribute, functions that
     are inside the scope of a `#pragma no_long_calls' directive and
     functions whose definitions have already been compiled within the
     current compilation unit, will not be turned into long calls.  The
     exception to this rule is that weak function definitions,
     functions with the `long-call' attribute or the `section'
     attribute, and functions that are within the scope of a `#pragma
     long_calls' directive, will always be turned into long calls.

     This feature is not enabled by default.  Specifying
     `-mno-long-calls' will restore the default behavior, as will
     placing the function calls within the scope of a `#pragma
     long_calls_off' directive.  Note these switches have no effect on
     how the compiler generates code to handle function calls via
     function pointers.

`-mnop-fun-dllimport'
     Disable support for the `dllimport' attribute.

`-msingle-pic-base'
     Treat the register used for PIC addressing as read-only, rather
     than loading it in the prologue for each function.  The run-time
     system is responsible for initializing this register with an
     appropriate value before execution begins.

`-mpic-register=REG'
     Specify the register to be used for PIC addressing.  The default
     is R10 unless stack-checking is enabled, when R9 is used.

`-mpoke-function-name'
     Write the name of each function into the text section, directly
     preceding the function prologue.  The generated code is similar to
     this:

               t0
                   .ascii "arm_poke_function_name", 0
                   .align
               t1
                   .word 0xff000000 + (t1 - t0)
               arm_poke_function_name
                   mov     ip, sp
                   stmfd   sp!, {fp, ip, lr, pc}
                   sub     fp, ip, #4

     When performing a stack backtrace, code can inspect the value of
     `pc' stored at `fp + 0'.  If the trace function then looks at
     location `pc - 12' and the top 8 bits are set, then we know that
     there is a function name embedded immediately preceding this
     location and has length `((pc[-3]) & 0xff000000)'.

`-mthumb'
     Generate code for the 16-bit Thumb instruction set.  The default
     is to use the 32-bit ARM instruction set.

`-mtpcs-frame'
     Generate a stack frame that is compliant with the Thumb Procedure
     Call Standard for all non-leaf functions.  (A leaf function is one
     that does not call any other functions.)  The default is
     `-mno-tpcs-frame'.

`-mtpcs-leaf-frame'
     Generate a stack frame that is compliant with the Thumb Procedure
     Call Standard for all leaf functions.  (A leaf function is one
     that does not call any other functions.)  The default is
     `-mno-apcs-leaf-frame'.

`-mcallee-super-interworking'
     Gives all externally visible functions in the file being compiled
     an ARM instruction set header which switches to Thumb mode before
     executing the rest of the function.  This allows these functions
     to be called from non-interworking code.

`-mcaller-super-interworking'
     Allows calls via function pointers (including virtual functions) to
     execute correctly regardless of whether the target code has been
     compiled for interworking or not.  There is a small overhead in
     the cost of executing a function pointer if this option is enabled.


File: gcc.info,  Node: MN10200 Options,  Next: MN10300 Options,  Prev: ARM Options,  Up: Submodel Options

MN10200 Options
---------------

   These `-m' options are defined for Matsushita MN10200 architectures:
`-mrelax'
     Indicate to the linker that it should perform a relaxation
     optimization pass to shorten branches, calls and absolute memory
     addresses.  This option only has an effect when used on the
     command line for the final link step.

     This option makes symbolic debugging impossible.


File: gcc.info,  Node: MN10300 Options,  Next: M32R/D Options,  Prev: MN10200 Options,  Up: Submodel Options

MN10300 Options
---------------

   These `-m' options are defined for Matsushita MN10300 architectures:

`-mmult-bug'
     Generate code to avoid bugs in the multiply instructions for the
     MN10300 processors.  This is the default.

`-mno-mult-bug'
     Do not generate code to avoid bugs in the multiply instructions
     for the MN10300 processors.

`-mam33'
     Generate code which uses features specific to the AM33 processor.

`-mno-am33'
     Do not generate code which uses features specific to the AM33
     processor.  This is the default.

`-mno-crt0'
     Do not link in the C run-time initialization object file.

`-mrelax'
     Indicate to the linker that it should perform a relaxation
     optimization pass to shorten branches, calls and absolute memory
     addresses.  This option only has an effect when used on the
     command line for the final link step.

     This option makes symbolic debugging impossible.


File: gcc.info,  Node: M32R/D Options,  Next: M88K Options,  Prev: MN10300 Options,  Up: Submodel Options

M32R/D Options
--------------

   These `-m' options are defined for Mitsubishi M32R/D architectures:

`-m32rx'
     Generate code for the M32R/X.

`-m32r'
     Generate code for the M32R.  This is the default.

`-mcode-model=small'
     Assume all objects live in the lower 16MB of memory (so that their
     addresses can be loaded with the `ld24' instruction), and assume
     all subroutines are reachable with the `bl' instruction.  This is
     the default.

     The addressability of a particular object can be set with the
     `model' attribute.

`-mcode-model=medium'
     Assume objects may be anywhere in the 32-bit address space (the
     compiler will generate `seth/add3' instructions to load their
     addresses), and assume all subroutines are reachable with the `bl'
     instruction.

`-mcode-model=large'
     Assume objects may be anywhere in the 32-bit address space (the
     compiler will generate `seth/add3' instructions to load their
     addresses), and assume subroutines may not be reachable with the
     `bl' instruction (the compiler will generate the much slower
     `seth/add3/jl' instruction sequence).

`-msdata=none'
     Disable use of the small data area.  Variables will be put into
     one of `.data', `bss', or `.rodata' (unless the `section'
     attribute has been specified).  This is the default.

     The small data area consists of sections `.sdata' and `.sbss'.
     Objects may be explicitly put in the small data area with the
     `section' attribute using one of these sections.

`-msdata=sdata'
     Put small global and static data in the small data area, but do not
     generate special code to reference them.

`-msdata=use'
     Put small global and static data in the small data area, and
     generate special instructions to reference them.

`-G NUM'
     Put global and static objects less than or equal to NUM bytes into
     the small data or bss sections instead of the normal data or bss
     sections.  The default value of NUM is 8.  The `-msdata' option
     must be set to one of `sdata' or `use' for this option to have any
     effect.

     All modules should be compiled with the same `-G NUM' value.
     Compiling with different values of NUM may or may not work; if it
     doesn't the linker will give an error message--incorrect code will
     not be generated.


File: gcc.info,  Node: M88K Options,  Next: RS/6000 and PowerPC Options,  Prev: M32R/D Options,  Up: Submodel Options

M88K Options
------------

   These `-m' options are defined for Motorola 88k architectures:

`-m88000'
     Generate code that works well on both the m88100 and the m88110.

`-m88100'
     Generate code that works best for the m88100, but that also runs
     on the m88110.

`-m88110'
     Generate code that works best for the m88110, and may not run on
     the m88100.

`-mbig-pic'
     Obsolete option to be removed from the next revision.  Use `-fPIC'.

`-midentify-revision'
     Include an `ident' directive in the assembler output recording the
     source file name, compiler name and version, timestamp, and
     compilation flags used.

`-mno-underscores'
     In assembler output, emit symbol names without adding an underscore
     character at the beginning of each name.  The default is to use an
     underscore as prefix on each name.

`-mocs-debug-info'
`-mno-ocs-debug-info'
     Include (or omit) additional debugging information (about
     registers used in each stack frame) as specified in the 88open
     Object Compatibility Standard, "OCS".  This extra information
     allows debugging of code that has had the frame pointer
     eliminated.  The default for DG/UX, SVr4, and Delta 88 SVr3.2 is
     to include this information; other 88k configurations omit this
     information by default.

`-mocs-frame-position'
     When emitting COFF debugging information for automatic variables
     and parameters stored on the stack, use the offset from the
     canonical frame address, which is the stack pointer (register 31)
     on entry to the function.  The DG/UX, SVr4, Delta88 SVr3.2, and
     BCS configurations use `-mocs-frame-position'; other 88k
     configurations have the default `-mno-ocs-frame-position'.

`-mno-ocs-frame-position'
     When emitting COFF debugging information for automatic variables
     and parameters stored on the stack, use the offset from the frame
     pointer register (register 30).  When this option is in effect,
     the frame pointer is not eliminated when debugging information is
     selected by the -g switch.

`-moptimize-arg-area'
     Save space by reorganizing the stack frame.  This option generates
     code that does not agree with the 88open specifications, but uses
     less memory.

`-mno-optimize-arg-area'
     Do not reorganize the stack frame to save space.  This is the
     default.  The generated conforms to the specification, but uses
     more memory.

`-mshort-data-NUM'
     Generate smaller data references by making them relative to `r0',
     which allows loading a value using a single instruction (rather
     than the usual two).  You control which data references are
     affected by specifying NUM with this option.  For example, if you
     specify `-mshort-data-512', then the data references affected are
     those involving displacements of less than 512 bytes.
     `-mshort-data-NUM' is not effective for NUM greater than 64k.

`-mserialize-volatile'
`-mno-serialize-volatile'
     Do, or don't, generate code to guarantee sequential consistency of
     volatile memory references.  By default, consistency is guaranteed.

     The order of memory references made by the MC88110 processor does
     not always match the order of the instructions requesting those
     references.  In particular, a load instruction may execute before
     a preceding store instruction.  Such reordering violates
     sequential consistency of volatile memory references, when there
     are multiple processors.   When consistency must be guaranteed,
     GCC generates special instructions, as needed, to force execution
     in the proper order.

     The MC88100 processor does not reorder memory references and so
     always provides sequential consistency.  However, by default, GCC
     generates the special instructions to guarantee consistency even
     when you use `-m88100', so that the code may be run on an MC88110
     processor.  If you intend to run your code only on the MC88100
     processor, you may use `-mno-serialize-volatile'.

     The extra code generated to guarantee consistency may affect the
     performance of your application.  If you know that you can safely
     forgo this guarantee, you may use `-mno-serialize-volatile'.

`-msvr4'
`-msvr3'
     Turn on (`-msvr4') or off (`-msvr3') compiler extensions related
     to System V release 4 (SVr4).  This controls the following:

       1. Which variant of the assembler syntax to emit.

       2. `-msvr4' makes the C preprocessor recognize `#pragma weak'
          that is used on System V release 4.

       3. `-msvr4' makes GCC issue additional declaration directives
          used in SVr4.

     `-msvr4' is the default for the m88k-motorola-sysv4 and
     m88k-dg-dgux m88k configurations.  `-msvr3' is the default for all
     other m88k configurations.

`-mversion-03.00'
     This option is obsolete, and is ignored.

`-mno-check-zero-division'
`-mcheck-zero-division'
     Do, or don't, generate code to guarantee that integer division by
     zero will be detected.  By default, detection is guaranteed.

     Some models of the MC88100 processor fail to trap upon integer
     division by zero under certain conditions.  By default, when
     compiling code that might be run on such a processor, GCC
     generates code that explicitly checks for zero-valued divisors and
     traps with exception number 503 when one is detected.  Use of
     `-mno-check-zero-division' suppresses such checking for code
     generated to run on an MC88100 processor.

     GCC assumes that the MC88110 processor correctly detects all
     instances of integer division by zero.  When `-m88110' is
     specified, no explicit checks for zero-valued divisors are
     generated, and both `-mcheck-zero-division' and
     `-mno-check-zero-division' are ignored.

`-muse-div-instruction'
     Use the div instruction for signed integer division on the MC88100
     processor.  By default, the div instruction is not used.

     On the MC88100 processor the signed integer division instruction
     div) traps to the operating system on a negative operand.  The
     operating system transparently completes the operation, but at a
     large cost in execution time.  By default, when compiling code
     that might be run on an MC88100 processor, GCC emulates signed
     integer division using the unsigned integer division instruction
     divu), thereby avoiding the large penalty of a trap to the
     operating system.  Such emulation has its own, smaller, execution
     cost in both time and space.  To the extent that your code's
     important signed integer division operations are performed on two
     nonnegative operands, it may be desirable to use the div
     instruction directly.

     On the MC88110 processor the div instruction (also known as the
     divs instruction) processes negative operands without trapping to
     the operating system.  When `-m88110' is specified,
     `-muse-div-instruction' is ignored, and the div instruction is used
     for signed integer division.

     Note that the result of dividing `INT_MIN' by -1 is undefined.  In
     particular, the behavior of such a division with and without
     `-muse-div-instruction' may differ.

`-mtrap-large-shift'
`-mhandle-large-shift'
     Include code to detect bit-shifts of more than 31 bits;
     respectively, trap such shifts or emit code to handle them
     properly.  By default GCC makes no special provision for large bit
     shifts.

`-mwarn-passed-structs'
     Warn when a function passes a struct as an argument or result.
     Structure-passing conventions have changed during the evolution of
     the C language, and are often the source of portability problems.
     By default, GCC issues no such warning.


File: gcc.info,  Node: RS/6000 and PowerPC Options,  Next: RT Options,  Prev: M88K Options,  Up: Submodel Options

IBM RS/6000 and PowerPC Options
-------------------------------

   These `-m' options are defined for the IBM RS/6000 and PowerPC:
`-mpower'
`-mno-power'
`-mpower2'
`-mno-power2'
`-mpowerpc'
`-mno-powerpc'
`-mpowerpc-gpopt'
`-mno-powerpc-gpopt'
`-mpowerpc-gfxopt'
`-mno-powerpc-gfxopt'
`-mpowerpc64'
`-mno-powerpc64'
     GCC supports two related instruction set architectures for the
     RS/6000 and PowerPC.  The "POWER" instruction set are those
     instructions supported by the `rios' chip set used in the original
     RS/6000 systems and the "PowerPC" instruction set is the
     architecture of the Motorola MPC5xx, MPC6xx, MPC8xx
     microprocessors, and the IBM 4xx microprocessors.

     Neither architecture is a subset of the other.  However there is a
     large common subset of instructions supported by both.  An MQ
     register is included in processors supporting the POWER
     architecture.

     You use these options to specify which instructions are available
     on the processor you are using.  The default value of these
     options is determined when configuring GCC.  Specifying the
     `-mcpu=CPU_TYPE' overrides the specification of these options.  We
     recommend you use the `-mcpu=CPU_TYPE' option rather than the
     options listed above.

     The `-mpower' option allows GCC to generate instructions that are
     found only in the POWER architecture and to use the MQ register.
     Specifying `-mpower2' implies `-power' and also allows GCC to
     generate instructions that are present in the POWER2 architecture
     but not the original POWER architecture.

     The `-mpowerpc' option allows GCC to generate instructions that
     are found only in the 32-bit subset of the PowerPC architecture.
     Specifying `-mpowerpc-gpopt' implies `-mpowerpc' and also allows
     GCC to use the optional PowerPC architecture instructions in the
     General Purpose group, including floating-point square root.
     Specifying `-mpowerpc-gfxopt' implies `-mpowerpc' and also allows
     GCC to use the optional PowerPC architecture instructions in the
     Graphics group, including floating-point select.

     The `-mpowerpc64' option allows GCC to generate the additional
     64-bit instructions that are found in the full PowerPC64
     architecture and to treat GPRs as 64-bit, doubleword quantities.
     GCC defaults to `-mno-powerpc64'.

     If you specify both `-mno-power' and `-mno-powerpc', GCC will use
     only the instructions in the common subset of both architectures
     plus some special AIX common-mode calls, and will not use the MQ
     register.  Specifying both `-mpower' and `-mpowerpc' permits GCC
     to use any instruction from either architecture and to allow use
     of the MQ register; specify this for the Motorola MPC601.

`-mnew-mnemonics'
`-mold-mnemonics'
     Select which mnemonics to use in the generated assembler code.
     With `-mnew-mnemonics', GCC uses the assembler mnemonics defined
     for the PowerPC architecture.  With `-mold-mnemonics' it uses the
     assembler mnemonics defined for the POWER architecture.
     Instructions defined in only one architecture have only one
     mnemonic; GCC uses that mnemonic irrespective of which of these
     options is specified.

     GCC defaults to the mnemonics appropriate for the architecture in
     use.  Specifying `-mcpu=CPU_TYPE' sometimes overrides the value of
     these option.  Unless you are building a cross-compiler, you
     should normally not specify either `-mnew-mnemonics' or
     `-mold-mnemonics', but should instead accept the default.

`-mcpu=CPU_TYPE'
     Set architecture type, register usage, choice of mnemonics, and
     instruction scheduling parameters for machine type CPU_TYPE.
     Supported values for CPU_TYPE are `rios', `rios1', `rsc', `rios2',
     `rs64a', `601', `602', `603', `603e', `604', `604e', `620', `630',
     `740', `7400', `7450', `750', `power', `power2', `powerpc', `403',
     `505', `801', `821', `823', and `860' and `common'.

     `-mcpu=common' selects a completely generic processor.  Code
     generated under this option will run on any POWER or PowerPC
     processor.  GCC will use only the instructions in the common
     subset of both architectures, and will not use the MQ register.
     GCC assumes a generic processor model for scheduling purposes.

     `-mcpu=power', `-mcpu=power2', `-mcpu=powerpc', and
     `-mcpu=powerpc64' specify generic POWER, POWER2, pure 32-bit
     PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
     types, with an appropriate, generic processor model assumed for
     scheduling purposes.

     The other options specify a specific processor.  Code generated
     under those options will run best on that processor, and may not
     run at all on others.

     The `-mcpu' options automatically enable or disable other `-m'
     options as follows:

    `common'
          `-mno-power', `-mno-powerc'

    `power'
    `power2'
    `rios1'
    `rios2'
    `rsc'
          `-mpower', `-mno-powerpc', `-mno-new-mnemonics'

    `powerpc'
    `rs64a'
    `602'
    `603'
    `603e'
    `604'
    `620'
    `630'
    `740'
    `7400'
    `7450'
    `750'
    `505'
          `-mno-power', `-mpowerpc', `-mnew-mnemonics'

    `601'
          `-mpower', `-mpowerpc', `-mnew-mnemonics'

    `403'
    `821'
    `860'
          `-mno-power', `-mpowerpc', `-mnew-mnemonics', `-msoft-float'

`-mtune=CPU_TYPE'
     Set the instruction scheduling parameters for machine type
     CPU_TYPE, but do not set the architecture type, register usage, or
     choice of mnemonics, as `-mcpu=CPU_TYPE' would.  The same values
     for CPU_TYPE are used for `-mtune' as for `-mcpu'.  If both are
     specified, the code generated will use the architecture,
     registers, and mnemonics set by `-mcpu', but the scheduling
     parameters set by `-mtune'.

`-maltivec'
`-mno-altivec'
     These switches enable or disable the use of built-in functions that
     allow access to the AltiVec instruction set.  You may also need to
     set `-mabi=altivec' to adjust the current ABI with AltiVec ABI
     enhancements.

`-mfull-toc'
`-mno-fp-in-toc'
`-mno-sum-in-toc'
`-mminimal-toc'
     Modify generation of the TOC (Table Of Contents), which is created
     for every executable file.  The `-mfull-toc' option is selected by
     default.  In that case, GCC will allocate at least one TOC entry
     for each unique non-automatic variable reference in your program.
     GCC will also place floating-point constants in the TOC.  However,
     only 16,384 entries are available in the TOC.

     If you receive a linker error message that saying you have
     overflowed the available TOC space, you can reduce the amount of
     TOC space used with the `-mno-fp-in-toc' and `-mno-sum-in-toc'
     options.  `-mno-fp-in-toc' prevents GCC from putting floating-point
     constants in the TOC and `-mno-sum-in-toc' forces GCC to generate
     code to calculate the sum of an address and a constant at run-time
     instead of putting that sum into the TOC.  You may specify one or
     both of these options.  Each causes GCC to produce very slightly
     slower and larger code at the expense of conserving TOC space.

     If you still run out of space in the TOC even when you specify
     both of these options, specify `-mminimal-toc' instead.  This
     option causes GCC to make only one TOC entry for every file.  When
     you specify this option, GCC will produce code that is slower and
     larger but which uses extremely little TOC space.  You may wish to
     use this option only on files that contain less frequently
     executed code.

`-maix64'
`-maix32'
     Enable 64-bit AIX ABI and calling convention: 64-bit pointers,
     64-bit `long' type, and the infrastructure needed to support them.
     Specifying `-maix64' implies `-mpowerpc64' and `-mpowerpc', while
     `-maix32' disables the 64-bit ABI and implies `-mno-powerpc64'.
     GCC defaults to `-maix32'.

`-mxl-call'
`-mno-xl-call'
     On AIX, pass floating-point arguments to prototyped functions
     beyond the register save area (RSA) on the stack in addition to
     argument FPRs.  The AIX calling convention was extended but not
     initially documented to handle an obscure K&R C case of calling a
     function that takes the address of its arguments with fewer
     arguments than declared.  AIX XL compilers access floating point
     arguments which do not fit in the RSA from the stack when a
     subroutine is compiled without optimization.  Because always
     storing floating-point arguments on the stack is inefficient and
     rarely needed, this option is not enabled by default and only is
     necessary when calling subroutines compiled by AIX XL compilers
     without optimization.

`-mpe'
     Support "IBM RS/6000 SP" "Parallel Environment" (PE).  Link an
     application written to use message passing with special startup
     code to enable the application to run.  The system must have PE
     installed in the standard location (`/usr/lpp/ppe.poe/'), or the
     `specs' file must be overridden with the `-specs=' option to
     specify the appropriate directory location.  The Parallel
     Environment does not support threads, so the `-mpe' option and the
     `-pthread' option are incompatible.

`-msoft-float'
`-mhard-float'
     Generate code that does not use (uses) the floating-point register
     set.  Software floating point emulation is provided if you use the
     `-msoft-float' option, and pass the option to GCC when linking.

`-mmultiple'
`-mno-multiple'
     Generate code that uses (does not use) the load multiple word
     instructions and the store multiple word instructions.  These
     instructions are generated by default on POWER systems, and not
     generated on PowerPC systems.  Do not use `-mmultiple' on little
     endian PowerPC systems, since those instructions do not work when
     the processor is in little endian mode.  The exceptions are PPC740
     and PPC750 which permit the instructions usage in little endian
     mode.

`-mstring'
`-mno-string'
     Generate code that uses (does not use) the load string instructions
     and the store string word instructions to save multiple registers
     and do small block moves.  These instructions are generated by
     default on POWER systems, and not generated on PowerPC systems.
     Do not use `-mstring' on little endian PowerPC systems, since those
     instructions do not work when the processor is in little endian
     mode.  The exceptions are PPC740 and PPC750 which permit the
     instructions usage in little endian mode.

`-mupdate'
`-mno-update'
     Generate code that uses (does not use) the load or store
     instructions that update the base register to the address of the
     calculated memory location.  These instructions are generated by
     default.  If you use `-mno-update', there is a small window
     between the time that the stack pointer is updated and the address
     of the previous frame is stored, which means code that walks the
     stack frame across interrupts or signals may get corrupted data.

`-mfused-madd'
`-mno-fused-madd'
     Generate code that uses (does not use) the floating point multiply
     and accumulate instructions.  These instructions are generated by
     default if hardware floating is used.

`-mno-bit-align'
`-mbit-align'
     On System V.4 and embedded PowerPC systems do not (do) force
     structures and unions that contain bit-fields to be aligned to the
     base type of the bit-field.

     For example, by default a structure containing nothing but 8
     `unsigned' bit-fields of length 1 would be aligned to a 4 byte
     boundary and have a size of 4 bytes.  By using `-mno-bit-align',
     the structure would be aligned to a 1 byte boundary and be one
     byte in size.

`-mno-strict-align'
`-mstrict-align'
     On System V.4 and embedded PowerPC systems do not (do) assume that
     unaligned memory references will be handled by the system.

`-mrelocatable'
`-mno-relocatable'
     On embedded PowerPC systems generate code that allows (does not
     allow) the program to be relocated to a different address at
     runtime.  If you use `-mrelocatable' on any module, all objects
     linked together must be compiled with `-mrelocatable' or
     `-mrelocatable-lib'.

`-mrelocatable-lib'
`-mno-relocatable-lib'
     On embedded PowerPC systems generate code that allows (does not
     allow) the program to be relocated to a different address at
     runtime.  Modules compiled with `-mrelocatable-lib' can be linked
     with either modules compiled without `-mrelocatable' and
     `-mrelocatable-lib' or with modules compiled with the
     `-mrelocatable' options.

`-mno-toc'
`-mtoc'
     On System V.4 and embedded PowerPC systems do not (do) assume that
     register 2 contains a pointer to a global area pointing to the
     addresses used in the program.

`-mlittle'
`-mlittle-endian'
     On System V.4 and embedded PowerPC systems compile code for the
     processor in little endian mode.  The `-mlittle-endian' option is
     the same as `-mlittle'.

`-mbig'
`-mbig-endian'
     On System V.4 and embedded PowerPC systems compile code for the
     processor in big endian mode.  The `-mbig-endian' option is the
     same as `-mbig'.

`-mcall-sysv'
     On System V.4 and embedded PowerPC systems compile code using
     calling conventions that adheres to the March 1995 draft of the
     System V Application Binary Interface, PowerPC processor
     supplement.  This is the default unless you configured GCC using
     `powerpc-*-eabiaix'.

`-mcall-sysv-eabi'
     Specify both `-mcall-sysv' and `-meabi' options.

`-mcall-sysv-noeabi'
     Specify both `-mcall-sysv' and `-mno-eabi' options.

`-mcall-aix'
     On System V.4 and embedded PowerPC systems compile code using
     calling conventions that are similar to those used on AIX.  This
     is the default if you configured GCC using `powerpc-*-eabiaix'.

`-mcall-solaris'
     On System V.4 and embedded PowerPC systems compile code for the
     Solaris operating system.

`-mcall-linux'
     On System V.4 and embedded PowerPC systems compile code for the
     Linux-based GNU system.

`-mcall-gnu'
     On System V.4 and embedded PowerPC systems compile code for the
     Hurd-based GNU system.

`-mcall-netbsd'
     On System V.4 and embedded PowerPC systems compile code for the
     NetBSD operating system.

`-maix-struct-return'
     Return all structures in memory (as specified by the AIX ABI).

`-msvr4-struct-return'
     Return structures smaller than 8 bytes in registers (as specified
     by the SVR4 ABI).

`-mabi=altivec'
     Extend the current ABI with AltiVec ABI extensions.  This does not
     change the default ABI, instead it adds the AltiVec ABI extensions
     to the current ABI.

`-mabi=no-altivec'
     Disable AltiVec ABI extensions for the current ABI.

`-mprototype'
`-mno-prototype'
     On System V.4 and embedded PowerPC systems assume that all calls to
     variable argument functions are properly prototyped.  Otherwise,
     the compiler must insert an instruction before every non
     prototyped call to set or clear bit 6 of the condition code
     register (CR) to indicate whether floating point values were
     passed in the floating point registers in case the function takes
     a variable arguments.  With `-mprototype', only calls to
     prototyped variable argument functions will set or clear the bit.

`-msim'
     On embedded PowerPC systems, assume that the startup module is
     called `sim-crt0.o' and that the standard C libraries are
     `libsim.a' and `libc.a'.  This is the default for
     `powerpc-*-eabisim'.  configurations.

`-mmvme'
     On embedded PowerPC systems, assume that the startup module is
     called `crt0.o' and the standard C libraries are `libmvme.a' and
     `libc.a'.

`-mads'
     On embedded PowerPC systems, assume that the startup module is
     called `crt0.o' and the standard C libraries are `libads.a' and
     `libc.a'.

`-myellowknife'
     On embedded PowerPC systems, assume that the startup module is
     called `crt0.o' and the standard C libraries are `libyk.a' and
     `libc.a'.

`-mvxworks'
     On System V.4 and embedded PowerPC systems, specify that you are
     compiling for a VxWorks system.

`-memb'
     On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags
     header to indicate that `eabi' extended relocations are used.

`-meabi'
`-mno-eabi'
     On System V.4 and embedded PowerPC systems do (do not) adhere to
     the Embedded Applications Binary Interface (eabi) which is a set of
     modifications to the System V.4 specifications.  Selecting `-meabi'
     means that the stack is aligned to an 8 byte boundary, a function
     `__eabi' is called to from `main' to set up the eabi environment,
     and the `-msdata' option can use both `r2' and `r13' to point to
     two separate small data areas.  Selecting `-mno-eabi' means that
     the stack is aligned to a 16 byte boundary, do not call an
     initialization function from `main', and the `-msdata' option will
     only use `r13' to point to a single small data area.  The `-meabi'
     option is on by default if you configured GCC using one of the
     `powerpc*-*-eabi*' options.

`-msdata=eabi'
     On System V.4 and embedded PowerPC systems, put small initialized
     `const' global and static data in the `.sdata2' section, which is
     pointed to by register `r2'.  Put small initialized non-`const'
     global and static data in the `.sdata' section, which is pointed
     to by register `r13'.  Put small uninitialized global and static
     data in the `.sbss' section, which is adjacent to the `.sdata'
     section.  The `-msdata=eabi' option is incompatible with the
     `-mrelocatable' option.  The `-msdata=eabi' option also sets the
     `-memb' option.

`-msdata=sysv'
     On System V.4 and embedded PowerPC systems, put small global and
     static data in the `.sdata' section, which is pointed to by
     register `r13'.  Put small uninitialized global and static data in
     the `.sbss' section, which is adjacent to the `.sdata' section.
     The `-msdata=sysv' option is incompatible with the `-mrelocatable'
     option.

`-msdata=default'
`-msdata'
     On System V.4 and embedded PowerPC systems, if `-meabi' is used,
     compile code the same as `-msdata=eabi', otherwise compile code the
     same as `-msdata=sysv'.

`-msdata-data'
     On System V.4 and embedded PowerPC systems, put small global and
     static data in the `.sdata' section.  Put small uninitialized
     global and static data in the `.sbss' section.  Do not use
     register `r13' to address small data however.  This is the default
     behavior unless other `-msdata' options are used.

`-msdata=none'
`-mno-sdata'
     On embedded PowerPC systems, put all initialized global and static
     data in the `.data' section, and all uninitialized data in the
     `.bss' section.

`-G NUM'
     On embedded PowerPC systems, put global and static items less than
     or equal to NUM bytes into the small data or bss sections instead
     of the normal data or bss section.  By default, NUM is 8.  The `-G
     NUM' switch is also passed to the linker.  All modules should be
     compiled with the same `-G NUM' value.

`-mregnames'
`-mno-regnames'
     On System V.4 and embedded PowerPC systems do (do not) emit
     register names in the assembly language output using symbolic
     forms.

`-pthread'
     Adds support for multithreading with the "pthreads" library.  This
     option sets flags for both the preprocessor and linker.


File: gcc.info,  Node: RT Options,  Next: MIPS Options,  Prev: RS/6000 and PowerPC Options,  Up: Submodel Options

IBM RT Options
--------------

   These `-m' options are defined for the IBM RT PC:

`-min-line-mul'
     Use an in-line code sequence for integer multiplies.  This is the
     default.

`-mcall-lib-mul'
     Call `lmul$$' for integer multiples.

`-mfull-fp-blocks'
     Generate full-size floating point data blocks, including the
     minimum amount of scratch space recommended by IBM.  This is the
     default.

`-mminimum-fp-blocks'
     Do not include extra scratch space in floating point data blocks.
     This results in smaller code, but slower execution, since scratch
     space must be allocated dynamically.

`-mfp-arg-in-fpregs'
     Use a calling sequence incompatible with the IBM calling
     convention in which floating point arguments are passed in
     floating point registers.  Note that `varargs.h' and `stdarg.h'
     will not work with floating point operands if this option is
     specified.

`-mfp-arg-in-gregs'
     Use the normal calling convention for floating point arguments.
     This is the default.

`-mhc-struct-return'
     Return structures of more than one word in memory, rather than in a
     register.  This provides compatibility with the MetaWare HighC (hc)
     compiler.  Use the option `-fpcc-struct-return' for compatibility
     with the Portable C Compiler (pcc).

`-mnohc-struct-return'
     Return some structures of more than one word in registers, when
     convenient.  This is the default.  For compatibility with the
     IBM-supplied compilers, use the option `-fpcc-struct-return' or the
     option `-mhc-struct-return'.

